Data Structures

Here are the data structures with brief descriptions:

[detail level 12]

►Nacia6850
Ct_control
Ct_receive_status
Ct_rx_if
Ct_rx_if_state
Ct_rxtx
Ct_transmit_if
Ct_transmit_status
Ct_tx_if
Ct_tx_if_state
►Napb_master_axi
Ct_axi_rd_state
Ct_axi_wr_state
►Napb_master_mux
Ct_arbiter_state
►Napb_processor
Ct_apb_combs
Ct_apb_state
Ct_processor_apb_request
Ct_processor_combs
Ct_processor_state
Ct_rom_combs
Ct_rom_state
►Napb_target_de1_cl_inputs
Ct_input_state
►Napb_target_gpio
Ct_gpio_input
Ct_gpio_output
►Napb_target_led_ws2812
Ct_chain_state
Ct_rgb
►Napb_target_ps2_host
Ct_ps2_state
►Napb_target_rv_timer
Ct_timer_combs
Ct_timer_state
►Napb_target_sram_interface
Ct_req_resp_state
►Napb_target_timer
Ct_timer
►Nbbc_display_sram
Ct_csrs
Ct_display_combs
Ct_display_state
Ct_sram_combs
Ct_sram_state
►Nbbc_floppy_sram
Ct_drive_combs
Ct_drive_state
Ct_floppy_combs
Ct_floppy_disk_state
Ct_floppy_state
Ct_sram_combs
Ct_sram_state
►Nbbc_keyboard_csr
Ct_csrs
Ct_keyboard_state
►Nbbc_keyboard_ps2
Ct_kbd_map_state
►Nbbc_micro
Ct_address_map_decoded
Ct_memory_access
►Nbbc_micro_clocking
Ct_clock_comb
Ct_control
Ct_divider
►Nbbc_micro_de1_cl_io
Ct_debug_combs
Ct_debug_state
Ct_key_state
►Nbbc_micro_rams
Ct_sram_inputs
►Nbbc_vidproc
Ct_control
Ct_palette_entry
►Ncpu6502
Ct_alu_result
Ct_data_path
Ct_flags
Ct_interrupt_state
Ct_ir_decode
Ct_mem_request
Ct_state
Ct_useq_decode
►Ncrtc6845
Ct_address_state
Ct_control
Ct_cursor_control
Ct_cursor_decode
Ct_horizontal_combs
Ct_horizontal_state
Ct_vertical_combs
Ct_vertical_state
►Ncsr_master_apb
Ct_apb_state
►Nde1_cl_controls
Ct_rotary_state
Ct_sr_combs
Ct_sr_state
►Ndprintf
Ct_byte_output_combs
Ct_data_buffer_state
Ct_decimal_combs
Ct_decimal_state
Ct_format_combs
Ct_format_state
►Nfdc8271
Ct_command
Ct_command_register
Ct_command_state
Ct_control
Ct_control_drive
Ct_control_scan
Ct_drive_execution
Ct_drive_execution_result
Ct_drive_execution_state
Ct_drive_operation
Ct_drive_operation_state
Ct_drive_outputs
Ct_drive_timing
Ct_drive_timing_state
Ct_parameter_register
Ct_result_register
Ct_set_outputs
Ct_status_register
►Nframebuffer
Ct_csrs
Ct_pixel_combs
Ct_pixel_shift_register
Ct_pixel_state
Ct_sram_state
►Nframebuffer_teletext
Ct_csrs
Ct_pixel_combs
Ct_pixel_shift_register
Ct_pixel_state
Ct_sram_state
Ct_video_csrs
Ct_video_state
►Nframebuffer_timing
Ct_csrs
Ct_video_combs
Ct_video_state
►Ngeneric_valid_ack_mux
Ct_arbiter_combs
Ct_arbiter_state
►Nhysteresis_switch
Ct_hysteresis_combs
Ct_hystersis_state
►Njtag_apb
Ct_apb_state
Ct_jtag_state
►Njtag_tap
Ct_jtag_combs
Ct_jtag_state
►Nled_ws2812_chain
Ct_data_chain_combs
Ct_data_chain_state
Ct_data_state
Ct_data_transmitter_combs
Ct_data_transmitter_state
Ct_drive_bits
►Npicoriscv
Ct_address_map_decoded
Ct_memory_access
►Nps2_host
Ct_clock_combs
Ct_clock_state
Ct_ps2_input_combs
Ct_ps2_input_state
Ct_ps2_receive_combs
Ct_ps2_receive_state
Ct_rx_result
►Nriscv_csrs_minimal
Ct_csr_write
►Nriscv_i32_alu
Ct_alu_combs
►Nriscv_i32_debug
Ct_apb_state
Ct_debug_combs
Ct_debug_state
Ct_dmstatus
►Nriscv_i32_decode
Ct_combs
►Nriscv_i32_muldiv
Ct_dec_fuse
Ct_dec_fuse_combs
Ct_dp_combs
Ct_dp_state
►Nriscv_i32_pipeline_debug
Ct_debug_combs
Ct_debug_state
►Nriscv_i32_trace
Ct_combs
►Nriscv_i32c_decode
Ct_combs
►Nriscv_i32c_pipeline
Ct_decexecrfw_combs
Ct_decexecrfw_state
Ct_ifetch_combs
►Nriscv_i32c_pipeline2
Ct_decexec_combs
Ct_decexec_state
Ct_rfw_combs
Ct_rfw_state
►Nriscv_i32c_pipeline3
Ct_alu_combs
Ct_alu_state
Ct_dec_combs
Ct_dec_state
Ct_ifetch_combs
Ct_mem_combs
Ct_mem_state
Ct_rfw_state
►Nriscv_jtag_apb_dm
Ct_apb_state
Ct_jtag_state
►Nriscv_simple
Ct_decexec_combs
Ct_decexec_state
Ct_rfw_combs
Ct_rfw_state
►Nsaa5050
Ct_load_state
Ct_pixel_state
►Nteletext
Ct_character_state
Ct_pixel_combs
Ct_pixel_state
Ct_teletext_combs
Ct_teletext_state
Ct_timing_state
►Nvia6522
Ct_acr
Ct_irq
Ct_pcr
Ct_port
Ct_port_edges
Ct_timer
Ct_timer_value
Ct_adv7123
Ct_apb_processor_request
Ct_apb_processor_response
Ct_apb_request
Ct_apb_response
Ct_apb_rom_request
Ct_axi_read_response
Ct_axi_request
Ct_axi_write_data
Ct_axi_write_response
Ct_bbc_clock_control
Ct_bbc_clock_status
Ct_bbc_display
Ct_bbc_display_sram_write
Ct_bbc_floppy_op
Ct_bbc_floppy_response
Ct_bbc_floppy_sector_id
Ct_bbc_floppy_sram_request
Ct_bbc_floppy_sram_response
Ct_bbc_keyboard
Ct_bbc_micro_sram_request
Ct_bbc_micro_sram_response
Ct_csr_access
Ct_csr_request
Ct_csr_response
Ct_de1_cl_diamond
Ct_de1_cl_inputs_control
Ct_de1_cl_inputs_status
Ct_de1_cl_joystick
Ct_de1_cl_lcd
Ct_de1_cl_rotary
Ct_de1_cl_shift_register
Ct_de1_cl_shift_register_control
Ct_de1_cl_user_inputs
Ct_de1_leds
Ct_dprintf_byte
Ct_dprintf_req_2
Ct_dprintf_req_4
Ct_dprintf_resp
Ct_jtag
Ct_led_ws2812_data
Ct_led_ws2812_request
Ct_prv_clock_control
Ct_prv_clock_status
Ct_prv_keyboard
Ct_prv_mem_control
Ct_ps2_key_state
Ct_ps2_pins
Ct_ps2_rx_data
Ct_riscv_config
Ct_riscv_csr_access
Ct_riscv_csr_controls
Ct_riscv_csr_data
Ct_riscv_csr_dcsr
Ct_riscv_csr_mie
Ct_riscv_csr_mip
Ct_riscv_csr_mstatus
Ct_riscv_csrs_minimal
Ct_riscv_debug_mst
Ct_riscv_debug_tgt
Ct_riscv_fetch_req
Ct_riscv_fetch_resp
Ct_riscv_i32_alu_result
Ct_riscv_i32_coproc_controls
Ct_riscv_i32_coproc_response
Ct_riscv_i32_decode
Ct_riscv_i32_decode_ext
Ct_riscv_i32_inst
Ct_riscv_i32_trace
Ct_riscv_irqs
Ct_riscv_mem_access_req
Ct_riscv_mem_access_resp
Ct_riscv_pipeline_debug_control
Ct_riscv_pipeline_debug_response
Ct_rotary_motion_inputs
Ct_sram_access_req
Ct_sram_access_resp
Ct_teletext_character
Ct_teletext_pixels
Ct_teletext_rom_access
Ct_teletext_timings
Ct_timer_control
Ct_timer_value
Ct_video_bus
Ct_video_timing