[in] | clk_2MHz | Supposedly 6MHz pixel clock (TR6), except we use 2MHz and deliver 3 pixels per tick; rising edge should be coincident with clk_1MHz edges |
[in] | clk_1MHz_enable | Clock enable high for clk_2MHz when the SAA's 1MHz would normally tick |
[in] | reset_n | Active low reset |
[in] | superimpose_n | Not implemented |
[in] | data_n | Serial data in, not implemented |
[in] | data_in | Parallel character data in |
[in] | dlim | Not implemented, clocks serial data in somehow |
[in] | glr | General line reset, can be tied to hsync - assert once per line before data comes in |
[in] | dew | Data entry window - used to determine flashing rate and resets the ROM decoders - can be tied to vsync |
[in] | crs | Character rounding select - drive high on even interlace fields to enable use of rounded character data (kinda indicates 'half line') |
[in] | bcs_n | Assert (low) to enable double-height characters (?) |
[out] | tlc_n | Asserted (low) when double-height characters occur (?) |
[in] | lose | Load output shift register enable - must be low before start of character data in a scanline, rising with (or one tick earlier?) the data; changes off falling F1, rising clk_1MHz |
[in] | de | Display enable |
[in] | po | Picture on |
[out] | red | Red pixels out, 6 per 2MHz clock tick |
[out] | green | Green pixels out, 6 per 2MHz clock tick |
[out] | blue | Blue pixels out, 6 per 2MHz clock tick |
[out] | blan | Not implemented |
[in] | host_sram_request | Write only, writes on clk_2MHz rising, acknowledge must be handled by supermodule |