framebuffer

Files
file	framebuffer.cdl
	Framebuffer module with separate display and video sides.

Detailed Description

Modules

module framebuffer::framebuffer	(	clock	csr_clk,
		clock	sram_clk,
		clock	video_clk,
		input bit	reset_n,
		input t_bbc_display_sram_write	display_sram_write,
		output t_video_bus	video_bus,
		input t_csr_request	csr_request,
		output t_csr_response	csr_response,
		input bit	csr_select[16]
	)

Parameters

[in]	csr_clk	Clock for CSR reads/writes
[in]	sram_clk	SRAM write clock, with frame buffer data
[in]	video_clk	Video clock, used to generate vsync, hsync, data out, etc
[in]	csr_select	This is a module that takes SRAM writes into a framebuffer, and includes a mapping to a dual-port SRAM (write on one side, read on the other), where the video side drives out vsync, hsync, data enable and pixel data.

The video side is asynchronous to the SRAM write side.

Video timing is handled by a framebuffer_timing module, which generates the synchronization signals and display enable. This module must be configure correctly for the display size and porches.

The video output start at a programmable base address in SRAM; moving down a line adds a programmable amount to the address in SRAM.

The module generates output pixel data from a shift register and a data buffer that fill from an internal dual-port SRAM, using the video timing.

The SRAM is filled with SRAM write requests, using a different clock to the video generation.

The current implementation is 1bpp RGB, with 16 pixels per SRAM word Bottom 16 SRAM data bits [16; 0] are red, bit[15] leftmost Next 16 SRAM data bits [16; 16] are green, bit[31] leftmost Top 16 SRAM data bits [16; 132] are blue, bit[47] leftmost