bbc_display_sram

Files
file	bbc_display_sram.cdl
	BBC micro display to SRAM write interface module.

Detailed Description

Modules

module bbc_display_sram::bbc_display_sram	(	clock	clk,
		input bit	reset_n,
		input t_bbc_display	display,
		output t_bbc_display_sram_write	sram_write,
		input t_csr_request	csr_request,
		output t_csr_response	csr_response
	)

Parameters

[in]	clk	Clock running at 2MHz
[out]	csr_response	This module mimics a monitor attached to the BBC video output, generating a stream of SRAM write requests as pixels are driven by the video output signals.

A regular video stream (from the BBC micro) runs at 2MHz with either 6 or 8 pixels per tick. On the BBC micro this is a pixel clock of either 16MHz or 12MHz.

The 't_bbc_display' indicates 1, 2, 4, 6 or 8 pixels per clock - but the interpretation here is for either 6 or 8 - since 1, 2 and 4 'pixels per clock' is the internal BBC pixels, which have been replicated on the bus. This should probably be fixed rather than explained.

The module is designed with a display input stage that manages vsync and hsync, and which then handles the 'back porch' for both vertical and horizontal blanking. The 'back porch' is the number of pixel clocks or scanlines that should not be captured following the detection of hsync/vsync respectively.

The display input stage then combines the input pixel data with the blanking for back porches to produce a validated pixel stream for the second stage of the module. Coupled to this are restart frame/line indicators.

For interlaced capture (which most monitors would be) the vsync will occur at different points in a line for even and odd fields. Even fields are SRAM addresses 0, 2, 4 (in 'line' terms), and odd fields are SRAM address 1, 3, 5 (again in 'line' terms). So the display input stage determines if a vsync corresponds to an odd or an even field.

The second stage is the SRAM data collation stage. This gathers the valid pixels from the display input stage into a shift register, and when 16 pixels are ready to be written they are passed to the SRAM write output stage. This SRAM data collation stage manages the SRAM addresses, resetting to the base address on a frame restart (plus a a single line of an odd field, interlaced), and incrementing the address on every write. A fixed number of SRAM writes is permitted per line (to set the captured display width). A fixed number of scanlines is permitted per frame (field).

Note that at the end of a line, for interlaced frames, the SRAM address is moved down by a line too, so that even fields do write to even 'lines' in SRAM, and odd lines just to the odd 'lines'.