CDL Modules
Data Structures
de1_cl.h File Reference

Input file for DE1 cl inputs and boards. More...

Detailed Description

Input file for DE1 cl inputs and boards.

Copyright (C) 2016-2017, Gavin J Stark. All rights reserved.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Header file for the types and CDL modules for input devices

Copyright (C) 2016-2017, Gavin J Stark. All rights reserved.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Header file for the types and CDL modules for input devices

From Martin Hinner's collection of data:

Timing values (display + (right border / front porch) + sync pulse + (back porch / left border))

640x480 @ 60Hz: 25.175MHz clk 640+16+ 96+48 = 800 480+10+2+33 = 525 -syncs 800x600 @ 60Hz: 40MHz clk 800+40+128+88 =1076 600+ 1+4+23 = 628 +syncs 1024x768 @ 60Hz: 65MHz clk 1024+24+136+160=1344 768+ 3+6+29 = 806 -syncs 1280x1024 @ 60Hz: 108MHz clk 1280+48+112+248=1688 1024+ 1+3+38 =1066 +syncs 1600x1200 @ 60Hz: 162MHz clk 1600+64+192+304=2160 1200+ 1+3+46 =1250 +syncs

Data Structures

struct  t_de1_cl_inputs_control
 
struct  t_rotary_motion_inputs
 
struct  t_de1_cl_inputs_status
 
struct  t_de1_cl_diamond
 
struct  t_de1_cl_joystick
 
struct  t_de1_cl_shift_register
 
struct  t_de1_cl_rotary
 
struct  t_de1_cl_user_inputs
 
struct  t_de1_cl_lcd
 
struct  t_de1_cl_shift_register_control
 
struct  t_de1_leds
 

Data Structure Documentation

struct t_de1_cl_inputs_control
Data Fields
bit sr_clock

Not really a clock in the FPGA, but a signal toggled by the design

bit sr_shift

Asserted high for rising sr_clock to shift the shift register; if low, the shift register is loaded from the pins

struct t_rotary_motion_inputs
Data Fields
bit direction_pin
bit transition_pin
struct t_de1_cl_inputs_status
Data Fields
t_rotary_motion_inputs left_rotary
t_rotary_motion_inputs right_rotary
bit sr_data

Shift register output data

struct t_de1_cl_diamond
Data Fields
bit a
bit b
bit x
bit y
struct t_de1_cl_joystick
Data Fields
bit c
bit d
bit l
bit r
bit u
struct t_de1_cl_shift_register
Data Fields
bit diall_click
bit dialr_click
t_de1_cl_diamond diamond
t_de1_cl_joystick joystick
bit temperature_alarm
bit touchpanel_irq
struct t_de1_cl_rotary
Data Fields
bit direction
bit direction_pulse
bit pressed
struct t_de1_cl_user_inputs
Data Fields
t_de1_cl_diamond diamond
t_de1_cl_joystick joystick
t_de1_cl_rotary left_dial
t_de1_cl_rotary right_dial
bit temperature_alarm
bit touchpanel_irq
bit updated_switches

Asserted if diamond, joystick, touchpanel_irq, temperature_alarm, and dial pressed bits have been updated

struct t_de1_cl_lcd
Data Fields
bit backlight
bit[6] blue
bit display_enable
bit[7] green
bit hsync_n
bit[6] red
bit vsync_n
struct t_de1_cl_shift_register_control
Data Fields
bit sr_clock
bit sr_shift
struct t_de1_leds
Data Fields
bit[7] h0
bit[7] h1
bit[7] h2
bit[7] h3
bit[7] h4
bit[7] h5
bit[10] leds

Modules

module bbc_micro_de1_cl_bbc ( clock  clk,
clock  video_clk,
input bit  reset_n,
input bit  bbc_reset_n,
input bit  framebuffer_reset_n,
output t_bbc_clock_control  clock_control,
input t_bbc_keyboard  bbc_keyboard,
output t_video_bus  video_bus,
input t_csr_request  csr_request,
output t_csr_response  csr_response 
)
Parameters
clk50MHz clock from DE1 clock generator
video_clk9MHz clock from PLL, derived from 50MHz
reset_nhard reset from a pin - a key on DE1
module bbc_micro_de1_cl_io ( clock  clk,
clock  video_clk,
input bit  reset_n,
input bit  bbc_reset_n,
input bit  framebuffer_reset_n,
input bit  keys[4],
input bit  switches[10],
input t_bbc_clock_control  clock_control,
output t_bbc_keyboard  bbc_keyboard,
output t_video_bus  video_bus,
output t_csr_request  csr_request,
input t_csr_response  csr_response,
input t_ps2_pins  ps2_in,
output t_ps2_pins  ps2_out,
input t_de1_cl_inputs_status  inputs_status,
output t_de1_cl_inputs_control  inputs_control,
output bit  leds[10],
output bit  lcd_source,
output bit  led_chain 
)
Parameters
clk50MHz clock from DE1 clock generator
video_clk9MHz clock from PLL, derived from 50MHz
reset_nhard reset from a pin - a key on DE1
ps2_inPS2 input pins
ps2_outPS2 output pin driver open collector
inputs_statusDE1 CL daughterboard shifter register etc status
inputs_controlDE1 CL daughterboard shifter register control
module de1_cl_controls ( clock  clk,
input bit  reset_n,
output t_de1_cl_inputs_control  inputs_control,
input t_de1_cl_inputs_status  inputs_status,
output t_de1_cl_user_inputs  user_inputs,
input bit  sr_divider[8] 
)
Parameters
[in]clksystem clock - not the shift register pin, something faster
[in]reset_nasync reset
[out]inputs_controlSignals to the shift register etc on the DE1 CL daughterboard
[in]inputs_statusSignals from the shift register, rotary encoders, etc on the DE1 CL daughterboard
[out]user_inputs
[in]sr_dividerclock divider to control speed of shift register