|
| enum | t_riscv_abi {
riscv_abi_zero = 0,
riscv_abi_link = 1,
riscv_abi_sp = 2
} |
| |
| enum | t_riscv_opc_rv32 {
riscv_opc_load = 0,
riscv_opc_load_fp = 1,
riscv_opc_custom_0 = 2,
riscv_opc_misc_mem = 3,
riscv_opc_op_imm = 4,
riscv_opc_auipc = 5,
riscv_opc_op_imm32 = 6,
riscv_opc_store = 8,
riscv_opc_store_fp = 9,
riscv_opc_custom_1 = 10,
riscv_opc_amo = 11,
riscv_opc_op = 12,
riscv_opc_lui = 13,
riscv_opc_op32 = 14,
riscv_opc_madd = 16,
riscv_opc_msub = 17,
riscv_opc_nmsub = 18,
riscv_opc_nmadd = 19,
riscv_opc_op_fp = 20,
riscv_opc_resvd_0 = 21,
riscv_opc_custom_2 = 22,
riscv_opc_branch = 24,
riscv_opc_jalr = 25,
riscv_opc_resvd_1 = 26,
riscv_opc_jal = 27,
riscv_opc_system = 28,
riscv_opc_resvd_2 = 29,
riscv_opc_custom_3 = 30
} |
| |
| enum | t_riscv_opc_rv32c {
riscv_opcc0_addi4spn = 0,
riscv_opcc0_lw = 2,
riscv_opcc0_sw = 6,
riscv_opcc1_addi = 0,
riscv_opcc1_jal = 1,
riscv_opcc1_li = 2,
riscv_opcc1_lui = 3,
riscv_opcc1_arith = 4,
riscv_opcc1_j = 5,
riscv_opcc1_beqz = 6,
riscv_opcc1_bnez = 7,
riscv_opcc2_slli = 0,
riscv_opcc2_lwsp = 2,
riscv_opcc2_misc_alu = 4,
riscv_opcc2_swsp = 6
} |
| |
| enum | t_riscv_system_f12 {
riscv_f12_ecall = 12h0,
riscv_f12_ebreak = 12h1,
riscv_f12_mret = 12h302,
riscv_f12_mwfi = 12h105
} |
| |
| enum | t_riscv_f3_alu {
riscv_f3_addsub = 0,
riscv_f3_sll = 1,
riscv_f3_slt = 2,
riscv_f3_sltu = 3,
riscv_f3_xor = 4,
riscv_f3_srlsra = 5,
riscv_f3_or = 6,
riscv_f3_and = 7
} |
| |
| enum | t_riscv_f3_muldiv {
riscv_f3_mul = 0,
riscv_f3_mulh = 1,
riscv_f3_mulhsu = 2,
riscv_f3_mulhu = 3,
riscv_f3_div = 4,
riscv_f3_divu = 5,
riscv_f3_rem = 6,
riscv_f3_remu = 7
} |
| |
| enum | t_riscv_f3_branch {
riscv_f3_beq = 0,
riscv_f3_bne = 1,
riscv_f3_blt = 4,
riscv_f3_bge = 5,
riscv_f3_bltu = 6,
riscv_f3_bgeu = 7
} |
| |
| enum | t_riscv_f3_load {
riscv_f3_lb = 0,
riscv_f3_lh = 1,
riscv_f3_lw = 2,
riscv_f3_lbu = 4,
riscv_f3_lhu = 5
} |
| |
| enum | t_riscv_f3_store {
riscv_f3_sb = 0,
riscv_f3_sh = 1,
riscv_f3_sw = 2
} |
| |
| enum | t_riscv_f3_misc_mem {
riscv_f3_fence = 0,
riscv_f3_fence_i = 1
} |
| |
| enum | t_riscv_f3_system {
riscv_f3_privileged = 0,
riscv_f3_csrrw = 1,
riscv_f3_csrrs = 2,
riscv_f3_csrrc = 3,
riscv_f3_csrrwi = 5,
riscv_f3_csrrsi = 6,
riscv_f3_csrrci = 7
} |
| |
| enum | t_riscv_mem_width {
mw_byte,
mw_half,
mw_word
} |
| |
| enum | t_riscv_op {
riscv_op_branch,
riscv_op_jal,
riscv_op_jalr,
riscv_op_system,
riscv_op_csr,
riscv_op_misc_mem,
riscv_op_load,
riscv_op_store,
riscv_op_alu,
riscv_op_muldiv,
riscv_op_auipc,
riscv_op_lui,
riscv_op_ext,
riscv_op_illegal
} |
| |
| enum | t_riscv_subop {
riscv_subop_valid =0,
riscv_subop_illegal = 0xf,
riscv_subop_beq =0,
riscv_subop_bne =1,
riscv_subop_blt =2,
riscv_subop_bge =3,
riscv_subop_bltu =4,
riscv_subop_bgeu =5,
riscv_subop_add = 0,
riscv_subop_sub = 0+8,
riscv_subop_sll = 1,
riscv_subop_slt = 2,
riscv_subop_sltu = 3,
riscv_subop_xor = 4,
riscv_subop_srl = 5,
riscv_subop_sra = 5+8,
riscv_subop_or = 6,
riscv_subop_and = 7,
riscv_subop_mull = 0,
riscv_subop_mulhss = 1,
riscv_subop_mulhsu = 2,
riscv_subop_mulhu = 3,
riscv_subop_divs = 4,
riscv_subop_divu = 5,
riscv_subop_rems = 6,
riscv_subop_remu = 7,
riscv_subop_lb = 0,
riscv_subop_lh = 1,
riscv_subop_lw = 2,
riscv_subop_lbu = 4,
riscv_subop_lhu = 5,
riscv_subop_sb = 0,
riscv_subop_sh = 1,
riscv_subop_sw = 2,
riscv_subop_ecall = 0,
riscv_subop_ebreak = 1,
riscv_subop_mret = 2,
riscv_subop_mwfi = 3,
riscv_subop_fence = 0,
riscv_subop_fence_i = 1,
riscv_subop_csrrw = 1,
riscv_subop_csrrs = 2,
riscv_subop_csrrc = 3
} |
| |
| enum | t_riscv_mcause {
riscv_mcause_instruction_misaligned = 0,
riscv_mcause_instruction_fault = 1,
riscv_mcause_illegal_instruction = 2,
riscv_mcause_breakpoint = 3,
riscv_mcause_load_misaligned = 4,
riscv_mcause_load_fault = 5,
riscv_mcause_store_misaligned = 6,
riscv_mcause_store_fault = 7,
riscv_mcause_uecall = 8,
riscv_mcause_secall = 9,
riscv_mcause_hecall = 10,
riscv_mcause_mecall = 11
} |
| |
| enum | t_riscv_trap_cause {
riscv_trap_cause_instruction_misaligned = 0,
riscv_trap_cause_instruction_fault = 1,
riscv_trap_cause_illegal_instruction = 2,
riscv_trap_cause_breakpoint = 3,
riscv_trap_cause_load_misaligned = 4,
riscv_trap_cause_load_fault = 5,
riscv_trap_cause_store_misaligned = 6,
riscv_trap_cause_store_fault = 7,
riscv_trap_cause_uecall = 8,
riscv_trap_cause_secall = 9,
riscv_trap_cause_hecall = 10,
riscv_trap_cause_mecall = 11
} |
| |
| enum | t_riscv_csr_access_type {
riscv_csr_access_none = 0,
riscv_csr_access_write = 1,
riscv_csr_access_read = 2,
riscv_csr_access_rw = 3,
riscv_csr_access_rs = 6,
riscv_csr_access_rc = 7
} |
| |
| enum | t_riscv_csr_addr {
CSR_ADDR_READWRITE_MASK = 12hc00,
CSR_ADDR_READ_WRITE_A = 12h000,
CSR_ADDR_READ_WRITE_B = 12h400,
CSR_ADDR_READ_WRITE_C = 12h800,
CSR_ADDR_READ_ONLY = 12hC00,
CSR_ADDR_MODE_MASK = 12h300,
CSR_ADDR_USER_MODE = 12h000,
CSR_ADDR_SUPERVISOR_MODE = 12h100,
CSR_ADDR_HYPERVISOR_MODE = 12h200,
CSR_ADDR_MACHINE_MODE = 12h300,
CSR_ADDR_USTATUS = 12h000,
CSR_ADDR_UIE = 12h004,
CSR_ADDR_UTVEC = 12h005,
CSR_ADDR_USCRATCH = 12h040,
CSR_ADDR_UEPC = 12h041,
CSR_ADDR_UCAUSE = 12h042,
CSR_ADDR_UTVAL = 12h043,
CSR_ADDR_UIP = 12h044,
CSR_ADDR_CYCLE = 12hC00,
CSR_ADDR_TIME = 12hC01,
CSR_ADDR_INSTRET = 12hC02,
CSR_ADDR_CYCLEH = 12hC80,
CSR_ADDR_TIMEH = 12hC81,
CSR_ADDR_INSTRETH = 12hC82,
CSR_ADDR_SSTATUS = 12h100,
CSR_ADDR_SEDELEG = 12h102,
CSR_ADDR_SIDELEG = 12h103,
CSR_ADDR_SIE = 12h104,
CSR_ADDR_STVEC = 12h105,
CSR_ADDR_SCOUNTEREN = 12h106,
CSR_ADDR_SSCRATCH = 12h140,
CSR_ADDR_SEPC = 12h141,
CSR_ADDR_SCAUSE = 12h142,
CSR_ADDR_SBADADDR = 12h143,
CSR_ADDR_SIP = 12h144,
CSR_ADDR_SPTBR = 12h180,
CSR_ADDR_MSTATUS = 12h300,
CSR_ADDR_MISA = 12h301,
CSR_ADDR_MEDELEG = 12h302,
CSR_ADDR_MIDELEG = 12h303,
CSR_ADDR_MIE = 12h304,
CSR_ADDR_MTVEC = 12h305,
CSR_ADDR_MCOUNTEREN = 12h306,
CSR_ADDR_MSCRATCH = 12h340,
CSR_ADDR_MEPC = 12h341,
CSR_ADDR_MCAUSE = 12h342,
CSR_ADDR_MTVAL = 12h343,
CSR_ADDR_MIP = 12h344,
CSR_ADDR_MCYCLE = 12hB00,
CSR_ADDR_MINSTRET = 12hB02,
CSR_ADDR_MCYCLEH = 12hB80,
CSR_ADDR_MINSTRETH = 12hB82,
CSR_ADDR_MVENDORID = 12hF11,
CSR_ADDR_MARCHID = 12hF12,
CSR_ADDR_MIMPID = 12hF13,
CSR_ADDR_MHARTID = 12hF14,
CSR_ADDR_DSCRATCH = 12h7B2
} |
| |
1.8.11
