csr_master_apb

Files
file	csr_master_apb.cdl
	Pipelined CSR request/response master, driven by an APB.

Detailed Description

Modules

module csr_master_apb::csr_master_apb	(	clock	clk,
		input bit	reset_n,
		input t_apb_request	apb_request,
		output t_apb_response	apb_response,
		input t_csr_response	csr_response,
		output t_csr_request	csr_request
	)

The documentation of the CSR interface itself is in other files (at this time, csr_target_csr.cdl).

This module drives a CSR interface in response to an incoming APB interface; it is an APB target presenting a CSR master interface. Its purpose is to permit an extension of an APB bus through a CSR target pipelined chain, hence providing for a timing-friendly CSR interface in an FPGA or ASIC.

The APB has a 32-bit paddr field, which is presented as 16 bits of CSR select and 16 bits of CSR address on the CSR interface. There is no timeout in this module on the CSR interface, so accesses to CSRs that have no responder on the bus will hang the module.

It is therefore wise to add a CSR target that detects very long transactions, and which responds by acknowledging them, to the CSR chain.

Parameters

[in]	clk	Clock for the APB and CSR interface; must be a superset of all targets clock
[in]	reset_n	Active low reset
[in]	apb_request	APB request from master
[out]	apb_response	APB response to master
[in]	csr_response	Pipelined csr request interface response
[out]	csr_request	Pipelined csr request interface output