riscv_i32_pipeline_debug

Files
file	riscv_i32_pipeline_debug.cdl
	Low-gate-count RISC-V pipeline debug module.

Detailed Description

Modules

module riscv_i32_pipeline_debug::riscv_i32_pipeline_debug	(	clock	clk,
		input bit	reset_n,
		input t_riscv_debug_mst	debug_mst,
		output t_riscv_debug_tgt	debug_tgt,
		output t_riscv_pipeline_debug_control	debug_control,
		input t_riscv_pipeline_debug_response	debug_response,
		input bit	rv_select[6]
	)

Parameters

[in]

rv_select

This is a fully synchronous pipeline debug module.

It is designed to feed data in to a RISC-V pipeline (being merged with instruction fetch responses), and it takes commands and reports out to a RISC-V debug module.