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CDL Modules
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Files | |
| file | riscv_i32_decode.cdl |
| Instruction decoder for RISC-V implementation. | |
| module riscv_i32_decode::riscv_i32_decode | ( | input t_riscv_i32_inst | instruction, |
| output t_riscv_i32_decode | idecode, | ||
| input t_riscv_config | riscv_config | ||
| ) |
| [in] | riscv_config | Instruction decoder for RISC-V I32 instruction set. |
This is based on the RISC-V v2.2 specification (hence figure numbers are from that specification)
It provides for the option of RV32E and RV32M.
RV32E indicates an illegal instruction if a register outside 0-15 is accessed.
RV32M provides decode of multiply and divide; if it is not desired then the instructions are decoded as illegal.
1.8.11