cpu6502

Files
file	cpu6502.cdl
	CDL implementation of 6502 CPU core.

Detailed Description

Modules

module cpu6502::cpu6502	(	clock	clk,
		input bit	reset_n,
		input bit	ready,
		input bit	irq_n,
		input bit	nmi_n,
		output bit	ba,
		output bit	address[16],
		output bit	read_not_write,
		output bit	data_out[8],
		input bit	data_in[8]
	)

Clock control logic - phase 0 is always one tick, phase 1 can be extended for reads by 'ready'

Decode 'ir' register (and other state, but not microsequencer)

Data path - drive buses, perform shift, inc/dec, ALU operations

Decimal flag set

Instruction started

pc

ir

acc

x

y

z

n

c

v

i

sp

Parameters

[in]	clk	Clock, rising edge is start of phi1, end of phi2 - the phi1/phi2 boundary is not required
[in]	ready	Stops processor during current instruction. Does not stop a write phase. Address bus reflects current address being read. Stops the phase 2 from happening.
[in]	irq_n	Active low interrupt in
[in]	nmi_n	Active low non-maskable interrupt in
[out]	ba	Goes high during phase 2 if ready was low in phase 1 if read_not_write is 1, to permit someone else to use the memory bus
[out]	address	In real 6502, changes during phi 1 with address to read or write
[out]	read_not_write	In real 6502, changes during phi 1 with whether to read or write
[out]	data_out	In real 6502, valid at end of phi2 with data to write
[in]	data_in	Captured at the end of phi2 (rising clock in here)