CDL Modules
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Files | |
file | framebuffer_teletext.cdl |
Teletext framebuffer module with separate write and video sides. | |
module framebuffer_teletext::framebuffer_teletext | ( | clock | csr_clk, |
clock | sram_clk, | ||
clock | video_clk, | ||
input bit | reset_n, | ||
input t_bbc_display_sram_write | display_sram_write, | ||
output t_video_bus | video_bus, | ||
input bit | csr_select_in[16], | ||
input t_csr_request | csr_request, | ||
output t_csr_response | csr_response | ||
) |
[in] | csr_clk | Clock for CSR reads/writes |
[in] | sram_clk | SRAM write clock, with frame buffer data |
[in] | video_clk | Video clock, used to generate vsync, hsync, data out, etc |
[out] | csr_response | This module provides a teletext framebuffer of configurable size. |
Each character is 12x10 pixels - horizontally smoothed, but not vertically.
This module incorporates a framebuffer_timing module which should be configured with the correct display size and porches; the csr_select used for this is 1 more than that used for this module itself.
The module includes a CSR target with two registers: framebuffer start address (register 0), and SRAM words per line (register 1). The words-per-line register should be initialized to the number of characters in a line (i.e. displayed pixels/12). The framebuffer start register can be used to have multiple framebuffers, or to provide for scrolling, or it can be held at 0.