framebuffer.h File Reference

Framebuffer CDL types and submodules. More...

Detailed Description

Framebuffer CDL types and submodules.

Copyright

(C) 2016-2017, Gavin J Stark. All rights reserved.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0. Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Header file for framebuffer modules for VGA, LCD panel, both bitmapped and teletext.

Data Structures
struct	t_video_timing

---

Data Structure Documentation

struct t_video_timing

Data Fields
bit	display_enable	Asserted if pixels should be presented to the output (i.e. outside the front and back porches both horizontally and vertically)
bit	display_required	Asserted for scanlines being displayed, up to the end of the horizontal displayed area - permits prefetching of pixel data
bit	h_sync	Asserted for a single clock at the start of every scanline
bit	v_displaying	Asserted for a scanline if the scanline will display data
bit	v_frame_last_line	Asserted if
bit	v_sync	Asserted for the whole of the first scanline or a frame
bit	will_display_enable	Asserted if the next clock will have display_enable asserted
bit	will_h_sync	Asserted if the next clock will be an h_sync

Modules

module framebuffer	(	clock	csr_clk,
		clock	sram_clk,
		clock	video_clk,
		input bit	reset_n,
		input t_bbc_display_sram_write	display_sram_write,
		output t_video_bus	video_bus,
		input t_csr_request	csr_request,
		output t_csr_response	csr_response,
		input bit	csr_select[16]
	)

Parameters

csr_clk	Clock for CSR reads/writes
sram_clk	SRAM write clock, with frame buffer data
video_clk	Video clock, used to generate vsync, hsync, data out, etc
csr_select	CSR select value to target this module on the CSR interface

module framebuffer_teletext	(	clock	csr_clk,
		clock	sram_clk,
		clock	video_clk,
		input bit	reset_n,
		input t_bbc_display_sram_write	display_sram_write,
		output t_video_bus	video_bus,
		input bit	csr_select_in[16],
		input t_csr_request	csr_request,
		output t_csr_response	csr_response
	)

Parameters

csr_clk	Clock for CSR reads/writes
sram_clk	SRAM write clock, with frame buffer data
video_clk	Video clock, used to generate vsync, hsync, data out, etc
csr_select_in	Tie to zero for default

module framebuffer_timing	(	clock	csr_clk,
		clock	video_clk,
		input bit	reset_n,
		output t_video_timing	video_timing,
		input t_csr_request	csr_request,
		output t_csr_response	csr_response,
		input bit	csr_select[16]
	)

Parameters

[in]	csr_clk	Clock for CSR reads/writes
[in]	video_clk	Video clock, used to generate vsync, hsync, data out, etc
[in]	reset_n	Active low reset
[out]	video_timing	Video timing outputs
[in]	csr_request	Pipelined CSR request interface to control the module
[out]	csr_response	Pipelined CSR response interface to control the module
[in]	csr_select	CSR select value to target this module on the CSR interface