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enum | t_src_enable {
src_en_acc = 0,
src_en_x = 1,
src_en_y = 2,
src_en_sp = 3,
src_en_psr = 4,
src_en_zero = 5,
src_en_pcl = 6,
src_en_pch = 7,
src_en_num = 8
} |
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enum | t_src_write_enable {
src_wr_en_acc = 0,
src_wr_en_x = 1,
src_wr_en_y = 2,
src_wr_en_sp = 3,
src_wr_en_psr = 4,
src_wr_en_flags = 5,
src_wr_en_num = 6
} |
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enum | t_ids_enable {
ids_en_pc = 0,
ids_en_src = 1,
ids_en_sp = 2,
ids_en_pch = 3,
ids_en_dl = 4,
ids_en_num = 5
} |
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enum | t_mem_data_src {
mem_data_src_src,
mem_data_src_pcl,
mem_data_src_pch,
mem_data_src_dl
} |
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enum | t_dl_src {
dl_src_data,
dl_src_alu,
dl_src_hold
} |
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enum | t_pc_op {
pc_op_hold,
pc_op_inc,
pc_op_branch_low,
pc_op_branch_high,
pc_op_jump,
pc_op_vector
} |
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enum | t_useq_cycle {
cycle_decode,
cycle_fetch,
cycle_alu_complete,
cycle_calc_zp_offset,
cycle_read_zp,
cycle_read_zp_inc_adl,
cycle_read_zp_adl_address_calc_index,
cycle_alu,
cycle_write_zp,
cycle_read_high,
cycle_dl_inc,
cycle_read_dl_adl,
cycle_write_dl_adl,
cycle_write_adh_adl,
cycle_read_pch_pcl_indirect,
cycle_read_dl_inc_pc,
cycle_read_pch_pcl,
cycle_push_src,
cycle_push_psr,
cycle_push_pch,
cycle_push_pcl,
cycle_inc_sp,
cycle_read_sp,
cycle_read_sp_psr_from_dl,
cycle_read_sp_to_pch_pcl,
cycle_bcc_pcl,
cycle_bcc_pch_bwd,
cycle_bcc_pch_fwd
} |
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enum | t_addressing_mode {
am_implied,
am_immediate,
am_zero_page,
am_absolute,
am_zero_indexed,
am_absolute_indexed,
am_indirect_x,
am_indirect_y,
am_branch,
am_brk,
am_rts,
am_rti,
am_jsr,
am_jump,
am_jump_indirect
} |
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enum | t_interrupt_reason {
interrupt_reason_reset =0,
interrupt_reason_nmi =1,
interrupt_reason_irq =2,
interrupt_reason_brk =3
} |
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enum | t_ids_op {
ids_op_lsl,
ids_op_rol,
ids_op_lsr,
ids_op_ror,
ids_op_pass,
ids_op_pass_2,
ids_op_dec,
ids_op_inc
} |
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enum | t_add_a_in_op {
add_a_in_op_pcl,
add_a_in_op_src,
add_a_in_op_zero
} |
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enum | t_add_b_in_op {
add_b_in_op_dl,
add_b_in_op_ids,
add_b_in_op_not_ids
} |
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enum | t_alu_op {
alu_op_or,
alu_op_and,
alu_op_bit,
alu_op_eor,
alu_op_a,
alu_op_b,
alu_op_adc,
alu_op_sbc,
alu_op_cmp,
alu_op_flags
} |
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