Files
file	riscv_i32_debug.cdl
	RISC-V debug module with APB interface.

Detailed Description

Modules

module riscv_i32_debug::riscv_i32_debug	(	clock	clk,
		input bit	reset_n,
		input t_apb_request	apb_request,
		output t_apb_response	apb_response,
		output t_riscv_debug_mst	debug_mst,
		input t_riscv_debug_tgt	debug_tgt
	)

This is a RISC-V debug module designed for the RV32I pipelines in the CDL hardware repo.

It provides the registers defined in the RISC-V Debug specificaiton revision 0.13.

Parameters