CDL Modules
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Types for the AXI bus. More...
Types for the AXI bus.
Copyright (C) 2018, Gavin J Stark. All rights reserved.
Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
Header file for the types for an AXI bus, but no modules
Data Structures | |
struct | t_axi_request |
struct | t_axi_write_data |
struct | t_axi_write_response |
struct | t_axi_read_response |
Enumerations | |
enum | t_axi_burst { axi_burst_fixed = 0, axi_burst_incr = 1, axi_burst_wrap = 2, axi_burst_reserved = 3 } |
enum | t_axi_size { axi_size_1 = 0, axi_size_2 = 1, axi_size_4 = 2, axi_size_8 = 3, axi_size_16 = 4, axi_size_32 = 5, axi_size_64 = 6, axi_size_128 = 7 } |
enum | t_axi_resp { axi_resp_okay = 0, axi_resp_exokay = 1, axi_resp_slverr = 2, axi_resp_decerr = 3 } |
struct t_axi_request |
Data Fields | ||
---|---|---|
bit[32] | addr | |
t_axi_burst | burst | |
bit[4] | cache | |
bit[12] | id | |
bit[4] | len | |
bit[2] | lock | |
bit[3] | prot | |
bit[4] | qos | |
bit[4] | region | |
t_axi_size | size | |
bit[4] | user | |
bit | valid |
struct t_axi_write_data |
struct t_axi_write_response |
Data Fields | ||
---|---|---|
bit[12] | id | |
t_axi_resp | resp | |
bit[4] | user | |
bit | valid |
struct t_axi_read_response |
This structure is used to store read response
Data Fields | ||
---|---|---|
bit[32] | data | |
bit[12] | id | |
bit | last | |
t_axi_resp | resp | |
bit[4] | user | |
bit | valid |
enum t_axi_burst |
enum t_axi_resp |
enum t_axi_size |
module axi_master | ( | clock | aclk, |
input bit | areset_n, | ||
output t_axi_request | ar, | ||
input bit | awready, | ||
output t_axi_request | aw, | ||
input bit | arready, | ||
input bit | wready, | ||
output t_axi_write_data | w, | ||
output bit | bready, | ||
input t_axi_write_response | b, | ||
output bit | rready, | ||
input t_axi_read_response | r | ||
) |