riscv_simple

Files
file	riscv_simple.cdl
	Very simple RISC-V implementation ported to CDL.

Detailed Description

Modules

module riscv_simple::riscv_simple	(	clock	clk,
		input bit	reset_n,
		output t_riscv_mem_access_req	dmem_access_req,
		input t_riscv_mem_access_resp	dmem_access_resp,
		output t_riscv_mem_access_req	imem_access_req,
		input t_riscv_mem_access_resp	imem_access_resp,
		output t_riscv_i32_trace	trace
	)

Parameters

[out]

trace

This processor tries to keep it as simple as possible, with a 3-stage pipeline.

The first stage is instruction fetch; the instruction memory request is put out just before the middle of the cycle, and a memory (running either at 2x the clock speed, or off the negedge of the clock) presents the instruction fetched at the end of the cycle, where it is registered.

The second stage takes the fetched instruction, decodes, fetches register values, and executes the ALU stage; determining in half a cycle the next instruction fetch, and in the whole cycle the data memory request, which is valid just before the end

Mem, CPU , imem_req.7 , imem_resp.9 , ifetch.0, decode.2, RF rd.5 , Exec , dmem_req.9 , dmem_resp.9 , RFW 0 , 0 , fetch A , X , , , , , , , 1 , 0 , - , inst A , , , , , , , 2 , 1 , fetch B , X , inst A , inst A , inst A , inst A, inst A , , 3 , 1 , , inst B , , , , , , inst A , inst A