Detailed Description

Modules

module riscv_i32c_pipeline::riscv_i32c_pipeline	(	clock	clk,
		input bit	reset_n,
		input t_riscv_irqs	irqs,
		output t_riscv_mem_access_req	dmem_access_req,
		input t_riscv_mem_access_resp	dmem_access_resp,
		output t_riscv_fetch_req	ifetch_req,
		input t_riscv_fetch_resp	ifetch_resp,
		output t_riscv_i32_coproc_controls	coproc_controls,
		input t_riscv_i32_coproc_response	coproc_response,
		input t_riscv_config	riscv_config,
		output t_riscv_i32_trace	trace
	)

Parameters

[in]	irqs	Interrupts in to the CPU
[out]	trace	This is just the processor pipeline, using a single stage for execution.

The instruction fetch request for the next cycle is put out just after the ALU stage logic, which may be a long time into the cycle; the fetch data response presents the instruction fetched at the end of the cycle, where it is registered for execution.

The pipeline is then a single stage that takes the fetched instruction, decodes, fetches register values, and executes the ALU stage; determining in half a cycle the next instruction fetch, and in the whole cycle the data memory request, which is valid just before the end

A coprocessor is supported; this may be configured to be disabled, in which case the outputs are driven low and the inputs are coprocessor response is ignored.

A coprocessor can implement, for example, the multiply for i32m (using riscv_i32_muldiv).