riscv.h File Reference

Header file for RISC-V implementations. More...

Detailed Description

Header file for RISC-V implementations.

Copyright

(C) 2016-2017, Gavin J Stark. All rights reserved.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0. Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Data Structures
struct	t_riscv_mem_access_req
struct	t_riscv_mem_access_resp
struct	t_riscv_irqs
struct	t_riscv_fetch_req
struct	t_riscv_fetch_resp
struct	t_riscv_config
struct	t_riscv_debug_mst
struct	t_riscv_debug_tgt
struct	t_riscv_pipeline_debug_control
struct	t_riscv_pipeline_debug_response

Typedefs
typedef bit[32]	t_riscv_word
typedef bit[2]	t_riscv_fetch_tag
typedef bit	t_riscv_debug_resp

Enumerations
enum	t_riscv_mode {   rv_mode_user = 3b000,   rv_mode_supervisor = 3b001,   rv_mode_machine = 3b011,   rv_mode_debug = 3b111 }
enum	t_riscv_debug_op {   rv_debug_set_requests,   rv_debug_read,   rv_debug_write,   rv_debug_acknowledge,   rv_debug_execute,   rv_debug_execute_progbuf }

Variables
constant integer	RISCV_DATA_ADDR_WIDTH = 14
constant integer	RISCV_INSTR_ADDR_WIDTH = 14

---

Data Structure Documentation

struct t_riscv_mem_access_req

Data Fields
bit[32]	address
bit[4]	byte_enable
bit	read_enable
bit[32]	write_data
bit	write_enable

struct t_riscv_mem_access_resp

Data Fields
bit[32]	read_data	Data returned from reading the requested address
bit	wait	Valid in the same cycle as read_data

struct t_riscv_irqs

Data Fields
bit	meip
bit	msip
bit	mtip
bit	nmi
bit	seip
bit[64]	time	Global time concept; may be tied low if user time CSR is not required
bit	ueip

struct t_riscv_fetch_req

Data Fields
bit[32]	address
bit	flush
t_riscv_mode	mode
bit	sequential
bit	valid

struct t_riscv_fetch_resp

Data Fields
bit[32]	data
bit	debug	Needs to permit register read/write encoding, break after execution, break before execution, execution mode, breakpoint-in-hardware-not-software; force-debug-subroutine-trap-before-execution
bit	error
t_riscv_mode	mode
t_riscv_fetch_tag	tag
bit	valid

struct t_riscv_config

Data Fields
bit	coproc_disable
bit	e32
bit	i32c
bit	i32m
bit	i32m_fuse
bit	unaligned_mem

struct t_riscv_debug_mst

Data Fields
bit[16]	arg	Argument for debug op
t_riscv_word	data	Data for writing or instruction execution
bit[6]	mask	PDM attention mask (mask && id)==(mask&&select) -> drive attention on next cycle
t_riscv_debug_op	op	Operation for selected PDM to perform
bit[6]	select	PDM to select
bit	valid	Asserted if op is valid; has no effect on mask and attention

struct t_riscv_debug_tgt

Data Fields
bit	attention	Asserted by a PDM if it has unacknowledged halt, breakpoint hit, resumption
t_riscv_word	data	Data from a completed transaction; 0 otherwise
bit	halted	Asserted by a PDM if it is selected and halted since last ack; 0 otherwise
bit	hit_breakpoint	Asserted by a PDM if it is selected and has hit breakpoint since lask ack; 0 otherwise
bit	op_was_none	Asserted if the response is not valid
t_riscv_debug_resp	resp	Response from a requested op - only one op should be requested for each response
bit	resumed	Asserted by a PDM if it is selected and has resumed since last ack; 0 otherwise
bit[6]	selected	Number of the PDM driving, or 0 if not driving the bus
bit	valid	Asserted by a PDM if driving the bus

struct t_riscv_pipeline_debug_control

Data Fields
t_riscv_word	data	Data from a completed transaction; 0 otherwise
bit	fetch_dret
bit	halt_request
bit	kill_fetch
bit	valid

struct t_riscv_pipeline_debug_response

Data Fields
bit	exec_dret
bit	exec_halting
bit	exec_valid

Typedef Documentation

typedef bit t_riscv_debug_resp

typedef bit [2] t_riscv_fetch_tag

typedef bit [32] t_riscv_word

Enumeration Type Documentation

enum t_riscv_debug_op

Enumerator
rv_debug_set_requests	Set request bits for halt, resume, step (args[0..2])
rv_debug_read	Request read of a GPR/CSR
rv_debug_write	Request write of a GPR/CSR
rv_debug_acknowledge	Acknowledge halt, breakpoint hit, status; removes attention signal
rv_debug_execute	Execute instruction provided resumption of execution at dpc and in mode dcsr.prv
rv_debug_execute_progbuf	Execute instruction at 'progbuf' address X (if it is a jump and link it will return)

enum t_riscv_mode

Enumerator
rv_mode_user
rv_mode_supervisor
rv_mode_machine
rv_mode_debug

Variable Documentation

constant integer RISCV_DATA_ADDR_WIDTH = 14

constant integer RISCV_INSTR_ADDR_WIDTH = 14