via6522

Files
file	via6522.cdl
	CDL implementation of a 6522 versatile interface adaptor (VIA)

Detailed Description

Modules

module via6522::via6522	(	clock	clk,
		clock	clk_io,
		input bit	reset_n,
		input bit	read_not_write,
		input bit	chip_select,
		input bit	chip_select_n,
		input bit	address[4],
		input bit	data_in[8],
		output bit	data_out[8],
		output bit	irq_n,
		input bit	ca1,
		input bit	ca2_in,
		output bit	ca2_out,
		output bit	pa_out[8],
		input bit	pa_in[8],
		input bit	cb1,
		input bit	cb2_in,
		output bit	cb2_out,
		output bit	pb_out[8],
		input bit	pb_in[8]
	)

Control registers

Parameters

[in]	clk	1MHz clock rising when bus cycle finishes
[in]	clk_io	1MHz clock rising when I/O should be captured - can be antiphase to clk
[in]	read_not_write	Indicates a read transaction if asserted and chip selected
[in]	chip_select	Active high chip select
[in]	chip_select_n	Active low chip select
[in]	address	Changes during phase 1 (phi[0] high) with address to read or write
[in]	data_in	Data in (from CPU)
[out]	data_out	Read data out (to CPU)
[out]	irq_n	Active low interrupt
[in]	ca1	Port a control 1 in
[in]	ca2_in	Port a control 2 in
[out]	ca2_out	Port a control 2 out
[out]	pa_out	Port a data out
[in]	pa_in	Port a data in
[in]	cb1	Port b control 1 in
[in]	cb2_in	Port b control 2 in
[out]	cb2_out	Port b control 2 out
[out]	pb_out	Port b data out
[in]	pb_in	Port b data in