CDL Modules
|
Files | |
file | riscv_simple.cdl |
Very simple RISC-V implementation ported to CDL. | |
module riscv_i32c_pipeline2::riscv_i32c_pipeline2 | ( | clock | clk, |
input bit | reset_n, | ||
input t_riscv_irqs | irqs, | ||
output t_riscv_mem_access_req | dmem_access_req, | ||
input t_riscv_mem_access_resp | dmem_access_resp, | ||
output t_riscv_fetch_req | ifetch_req, | ||
input t_riscv_fetch_resp | ifetch_resp, | ||
input t_riscv_config | riscv_config, | ||
output t_riscv_i32_trace | trace | ||
) |
[in] | irqs | Interrupts in to the CPU |
[out] | trace |