apb_target_sram_interface

Files
file	apb_target_sram_interface.cdl
	APB bus target to drive an SRAM read/write request.

Detailed Description

Modules

module apb_target_sram_interface::apb_target_sram_interface	(	clock	clk,
		input bit	reset_n,
		input t_apb_request	apb_request,
		output t_apb_response	apb_response,
		output bit	sram_ctrl[32],
		output t_sram_access_req	sram_access_req,
		input t_sram_access_resp	sram_access_resp
	)

APB target peripheral that generates SRAM read/write requests

The module maintains a 32-bit SRAM address that is used in the requests, which is a read/write register. There is also a 32-bit control register, that can be used for any purpose by the client.

SRAM requests occur when the data register is accessed; it can be accessed in one of three different ways. Firstly, it may be accessed simply read/write, with either generating the appropriate SRAM request to the address given by the SRAM address register. Secondly, it may be accessed with a post-increment, where the SRAM address register value is used as-is in the request, but it is incremented ready for a subsequent transaction. Thirdly, it may be accessed 'windowed'; in this manner the bottom 7 bits of the APB address are used in conjunction with the top 25 bits of the SRAM address register to generate the address for the SRAM request.

Parameters

[in]	clk	System clock
[in]	reset_n	Active low reset
[in]	apb_request	APB request
[out]	apb_response	APB response
[out]	sram_ctrl	SRAM control data, for whatever purpose
[out]	sram_access_req	SRAM access request
[in]	sram_access_resp	SRAM access response