acia6850

Files
file	acia6850.cdl
	6850 async communications chip CDL implementation

Detailed Description

Modules

module acia6850::acia6850	(	clock	clk,
		input bit	reset_n,
		input bit	read_not_write,
		input bit	chip_select[2],
		input bit	chip_select_n,
		input bit	address,
		input bit	data_in[8],
		output bit	data_out[8],
		output bit	irq_n,
		input bit	tx_clk,
		input bit	rx_clk,
		output bit	txd,
		input bit	cts,
		input bit	rxd,
		output bit	rts,
		input bit	dcd
	)

Parameters

[in]	clk	Clock that rises when the 'enable' of the 6850 completes - but a real clock for this model
[in]	read_not_write	Indicates a read transaction if asserted and chip selected
[in]	chip_select	Active high chip select
[in]	chip_select_n	Active low chip select
[in]	address	Changes during phase 1 (phi[0] high) with address to read or write
[in]	data_in	Data in (from CPU)
[out]	data_out	Read data out (to CPU)
[out]	irq_n	Active low interrupt
[in]	tx_clk	Clock used for transmit data - must be really about at most quarter the speed of clk
[in]	rx_clk	Clock used for receive data - must be really about at most quarter the speed of clk