generic_valid_ack_mux

Files
file	generic_valid_ack_mux.cdl
	A generic valid/ack multiplexer to combine buses with valid/ack protocol.

Detailed Description

Modules

module generic_valid_ack_mux::generic_valid_ack_mux	(	clock	clk,
		input bit	reset_n,
		input gt_generic_valid_req	req_a,
		input gt_generic_valid_req	req_b,
		output bit	ack_a,
		output bit	ack_b,
		output gt_generic_valid_req	req,
		input bit	ack
	)

Generic multiplexer for two identical requesters (with a valid signal each), to arbitrate for an output request, with a response with an 'ack' signal.

This module may be used with a different type (using type remapping) to generate a specific multiplexer for two validated requests, which have just an ack in response (e.g. the teletext dprintf requests).

The module registers its output request; it remembers which requester it consumed from last, and will preferentially consue from the other port next - hence supplying some degree of fairness.

When its output is not valid, or is being acknowledged, it may take a new request from one of the two requesting masters, using the desired priority. It will also then acknowledge that requester.

If its output is valid and is not acknowledged, then it will not consumer another request.

Parameters

[in]	clk	Clock for logic
[in]	reset_n	Active low reset
[in]	req_a	Request from upstream 'A' port, which must have a valid bit
[in]	req_b	Request from upstream 'B' port, which must have a valid bit
[out]	ack_a	Acknowledge to upstream 'A' port
[out]	ack_b	Acknowledge to upstream 'B' port
[out]	req	Request out downstream, which must have a valid bit
[in]	ack	Acknowledge from downstream