CDL Modules
Files
ps2_host

Files

file  ps2_host.cdl
 PS2 interface for keyboard or mouse.
 

Detailed Description

Modules

module ps2_host::ps2_host ( clock  clk,
input bit  reset_n,
input t_ps2_pins  ps2_in,
output t_ps2_pins  ps2_out,
output t_ps2_rx_data  ps2_rx_data,
input bit  divider[16] 
)

As a PS2 host, to receive data from the slave (the first target for the design), the module:

  1. Looks for clock falling
  2. If data is low, then assume this is a start bit. Set timeout timer.
  3. Wait for clock falling. Clock in data bit 0
  4. Wait for clock falling. Clock in data bit 1
  5. Wait for clock falling. Clock in data bit 2
  6. Wait for clock falling. Clock in data bit 3
  7. Wait for clock falling. Clock in data bit 4
  8. Wait for clock falling. Clock in data bit 5
  9. Wait for clock falling. Clock in data bit 6
  10. Wait for clock falling. Clock in data bit 7
  11. Wait for clock falling. Clock in parity bit.
  12. Wait for clock falling. Clock in stop bit.
  13. Wait for clock high.
  14. Validate data (stop bit 1, parity correct)

If a timeout timer expires, which could happen if the framing is bad, then an abort can be taken.

Parameters
[in]clkClock
[in]reset_nActive low reset
[in]ps2_inPin values from the outside
[out]ps2_outPin values to drive - 1 means float high, 0 means pull low
[out]ps2_rx_dataPS2 receive data from the device, in parallel
[in]dividerClock divider input to generate approx 3us from clk