As a PS2 host, to receive data from the slave (the first target for the design), the module:
- Looks for clock falling
- If data is low, then assume this is a start bit. Set timeout timer.
- Wait for clock falling. Clock in data bit 0
- Wait for clock falling. Clock in data bit 1
- Wait for clock falling. Clock in data bit 2
- Wait for clock falling. Clock in data bit 3
- Wait for clock falling. Clock in data bit 4
- Wait for clock falling. Clock in data bit 5
- Wait for clock falling. Clock in data bit 6
- Wait for clock falling. Clock in data bit 7
- Wait for clock falling. Clock in parity bit.
- Wait for clock falling. Clock in stop bit.
- Wait for clock high.
- Validate data (stop bit 1, parity correct)
If a timeout timer expires, which could happen if the framing is bad, then an abort can be taken.
- Parameters
-
[in] | clk | Clock |
[in] | reset_n | Active low reset |
[in] | ps2_in | Pin values from the outside |
[out] | ps2_out | Pin values to drive - 1 means float high, 0 means pull low |
[out] | ps2_rx_data | PS2 receive data from the device, in parallel |
[in] | divider | Clock divider input to generate approx 3us from clk |