- c -

• cfg_downsize_x : dprintf , framebuffer_teletext
• cfg_downsize_y : dprintf , framebuffer_teletext
• coproc_force_disable : riscv_i32c_pipeline3 , riscv_i32c_pipeline
• csr_select_default : framebuffer_teletext

- d -

• divider_400ns : bbc_micro_de1_cl_io , hps_fpga_debug
• dr_length : jtag_tap

- e -

• e32_force_enable : riscv_i32_decode , riscv_i32c_decode

- f -

• fifo_size : apb_target_ps2_host
• filter_level : de1_cl_controls
• filter_period : de1_cl_controls
• flashing_on_count : teletext

- i -

• i32_custom0_enable : riscv_i32_decode
• i32_custom1_enable : riscv_i32_decode
• i32_custom2_enable : riscv_i32_decode
• i32_custom3_enable : riscv_i32_decode
• i32c_force_disable : riscv_i32_minimal , riscv_i32c_pipeline2 , riscv_i32c_pipeline3 , riscv_i32c_pipeline
• i32m_force_disable : riscv_i32_decode
• i32m_fuse_force_disable : riscv_i32_muldiv
• INITIAL_PC : riscv_i32c_pipeline2 , riscv_i32c_pipeline3 , riscv_i32c_pipeline , riscv_simple
• ir_length : jtag_tap

- j -

• jtag_idcode : jtag_apb , riscv_jtag_apb_dm

- l -

• lg_fifo_size : apb_target_ps2_host

- m -

• max_flashing_count : teletext
• max_hart_minus_one : riscv_i32_debug
• max_length : jtag_tap
• mhartid : riscv_csrs_minimal
• mimpid : riscv_csrs_minimal
• misa : riscv_csrs_minimal
• mstatus : riscv_csrs_minimal
• mvendorid : riscv_csrs_minimal

- n -

• num_dprintf_requesters : bbc_micro_de1_cl_io , hps_fpga_debug

- p -

• pixel_counter_width : bbc_display_sram

- s -

• sr_divider : bbc_micro_de1_cl_io , hps_fpga_debug
• sr_length : de1_cl_controls

- t -

• timeout_rx_data : ps2_host
• timer_10us_counter_value : fdc8271
• timer_1ms_counter_value : fdc8271
• timer_data_counter_value : fdc8271

- v -

• valid_hart_mask : riscv_i32_debug