riscv_i32_minimal

Detailed Description

Modules

module riscv_i32_minimal::riscv_i32_minimal	(	clock	clk,
		input bit	reset_n,
		input bit	proc_reset_n,
		input t_riscv_irqs	irqs,
		output t_riscv_mem_access_req	data_access_req,
		input t_riscv_mem_access_resp	data_access_resp,
		input t_sram_access_req	sram_access_req,
		output t_sram_access_resp	sram_access_resp,
		input t_riscv_config	riscv_config,
		output t_riscv_i32_trace	trace
	)

Parameters

[in]	irqs	Interrupts in to the CPU
[out]	trace	An instantiation of the single stage pipeline RISC-V with RV32I with a single SRAM

Compressed instructions are supported IF i32c_force_disable is 0 and riscv_config.i32c is 1

A single memory is used for instruction and data, at address 0

Any access outside of the bottom 1MB is passed as a request out of this module.