- m -

• mask : t_riscv_debug_mst
• match : riscv_i32_muldiv::t_dec_fuse_combs
• max_scan_line : crtc6845::t_vertical_combs
• mcause : t_riscv_csrs_minimal
• meie : t_riscv_csr_mie
• meip : t_riscv_csr_mip , t_riscv_irqs
• mem_data_out : cpu6502::t_data_path
• mem_data_src : cpu6502::t_useq_decode
• mem_request : cpu6502::t_useq_decode
• mem_result : riscv_i32c_pipeline3::t_rfw_state
• memory_address : crtc6845::t_address_state
• memory_address_line_start : crtc6845::t_address_state
• memory_data : riscv_i32c_pipeline2::t_rfw_combs , riscv_i32c_pipeline3::t_mem_combs , riscv_i32c_pipeline::t_decexecrfw_combs , riscv_simple::t_rfw_combs
• memory_read : cpu6502::t_ir_decode , riscv_i32c_pipeline2::t_rfw_state , riscv_simple::t_decexec_combs , riscv_simple::t_rfw_state
• memory_read_unsigned : t_riscv_i32_decode
• memory_width : t_riscv_i32_decode
• memory_write : cpu6502::t_ir_decode , riscv_simple::t_decexec_combs
• mepc : t_riscv_csrs_minimal
• mie : t_riscv_csr_mstatus
• mode : crtc6845::t_cursor_control , t_riscv_fetch_req , t_riscv_fetch_resp , t_riscv_i32_inst
• mpie : t_riscv_csr_mstatus
• mpp : t_riscv_csr_mstatus
• mprv : t_riscv_csr_mstatus
• mprven : t_riscv_csr_dcsr
• mret : riscv_i32c_pipeline3::t_alu_combs
• msb : fdc8271::t_control_scan
• mscratch : t_riscv_csrs_minimal
• msie : t_riscv_csr_mie
• msip : t_riscv_csr_mip , t_riscv_irqs
• mst_valid : riscv_i32_pipeline_debug::t_debug_combs
• mtie : t_riscv_csr_mie
• mtip : t_riscv_csr_mip , t_riscv_irqs
• mtval : t_riscv_csrs_minimal
• mtvec : t_riscv_csrs_minimal
• mult_data : riscv_i32_muldiv::t_dp_combs
• mult_shf : riscv_i32_muldiv::t_dp_combs
• must_be_ones : riscv_i32_decode::t_combs , riscv_i32_trace::t_combs
• must_set_requests : riscv_i32_debug::t_debug_state
• mux_0123 : riscv_i32_muldiv::t_dp_combs
• mux_048c : riscv_i32_muldiv::t_dp_combs
• mxr : t_riscv_csr_mstatus