- h -

• h0 : t_de1_leds
• h1 : t_de1_leds
• h2 : t_de1_leds
• h3 : t_de1_leds
• h4 : t_de1_leds
• h5 : t_de1_leds
• h_back_porch : bbc_display_sram::t_csrs , framebuffer_teletext::t_video_csrs , framebuffer_timing::t_csrs
• h_back_porch_end : framebuffer_timing::t_video_combs
• h_display : framebuffer_teletext::t_video_csrs , framebuffer_timing::t_csrs
• h_display_end : framebuffer_timing::t_video_combs
• h_displayed : crtc6845::t_control
• h_displaying : framebuffer_timing::t_video_combs
• h_front_porch : framebuffer_teletext::t_video_csrs , framebuffer_timing::t_csrs
• h_line_end : framebuffer_timing::t_video_combs
• h_line_start : framebuffer_timing::t_video_combs
• h_pixel : framebuffer_timing::t_video_state
• h_state : framebuffer_timing::t_video_state
• h_sync : framebuffer_timing::t_video_state , t_video_timing
• h_sync_pos : crtc6845::t_control
• h_sync_width : crtc6845::t_control
• h_total : crtc6845::t_control
• h_will_be_displaying : framebuffer_timing::t_video_combs
• halfway : crtc6845::t_horizontal_combs
• halt_req : riscv_i32_debug::t_debug_state , riscv_i32_pipeline_debug::t_debug_state
• halt_request : t_riscv_pipeline_debug_control
• halted : riscv_i32_debug::t_debug_state , riscv_i32_pipeline_debug::t_debug_state , t_riscv_debug_tgt
• halted_all : riscv_i32_debug::t_dmstatus
• halted_any : riscv_i32_debug::t_dmstatus
• haltsum0 : riscv_i32_debug::t_debug_combs
• haltsum1 : riscv_i32_debug::t_debug_combs
• handling : apb_master_mux::t_arbiter_state
• hart_sel : riscv_i32_debug::t_debug_state
• hart_sel_mask : riscv_i32_debug::t_debug_combs
• hart_to_poll : riscv_i32_debug::t_debug_state
• has_expired : via6522::t_timer
• has_reset_halt_req : riscv_i32_debug::t_dmstatus
• have_reset_all : riscv_i32_debug::t_dmstatus
• have_reset_any : riscv_i32_debug::t_dmstatus
• head : t_bbc_floppy_sector_id
• head_counter : fdc8271::t_drive_timing_state
• head_load_time : fdc8271::t_control
• head_settled : fdc8271::t_drive_timing
• head_settling_time : fdc8271::t_control
• head_timer_4ms : fdc8271::t_drive_timing
• head_unload_count : fdc8271::t_control
• held_graphics_data : teletext::t_pixel_state
• hex_bottom_nybble : dprintf::t_format_combs
• hex_top_nybble : dprintf::t_format_combs
• high : via6522::t_timer_value
• hit_breakpoint : riscv_i32_debug::t_debug_state , riscv_i32_pipeline_debug::t_debug_state , t_riscv_debug_tgt
• hold_graphics_mode : teletext::t_character_state
• hs : t_adv7123
• hsync : t_bbc_display , t_video_bus
• hsync_detected : bbc_display_sram::t_display_combs
• hsync_n : t_de1_cl_lcd