|
CDL Modules
|
Files | |
| file | riscv_csrs_minimal.cdl |
| Control/status registers for a minimal RISC-V implementation. | |
| file | riscv_e32_decode.cdl |
| file | riscv_e32c_decode.cdl |
| file | riscv_i32_alu.cdl |
| ALU for i32 RISC-V implementation. | |
| file | riscv_i32_debug.cdl |
| RISC-V debug module with APB interface. | |
| file | riscv_i32_decode.cdl |
| Instruction decoder for RISC-V implementation. | |
| file | riscv_i32_fetch_debug.cdl |
| Instruction fetch interposer for debug. | |
| file | riscv_i32_minimal.cdl |
| file | riscv_i32_minimal_apb.cdl |
| file | riscv_i32_muldiv.cdl |
| file | riscv_i32_pipeline_debug.cdl |
| Low-gate-count RISC-V pipeline debug module. | |
| file | riscv_i32_trace.cdl |
| Instruction trace for RISC-V implementation. | |
| file | riscv_i32c_decode.cdl |
| Instruction decoder for RISC-V implementation. | |
| file | riscv_i32c_pipeline.cdl |
| file | riscv_i32c_pipeline2.cdl |
| file | riscv_i32c_pipeline3.cdl |
| file | riscv_jtag_apb_dm.cdl |
| file | riscv_minimal_debug.cdl |
| file | riscv_simple.cdl |
| Very simple RISC-V implementation ported to CDL. | |
1.8.11