riscv_i32_decode.cdl File Reference

Instruction decoder for RISC-V implementation. More...

Detailed Description

Instruction decoder for RISC-V implementation.

Copyright

(C) 2016-2017, Gavin J Stark. All rights reserved.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0. Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

CDL implementation of RISC-V instruction decode based on the RISC-V specification v2.1.

Copyright

(C) 2016-2017, Gavin J Stark. All rights reserved.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0. Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

CDL implementation of RISC-V instruction decode based on the RISC-V specification v2.2.

Data Structures
struct	riscv_i32_decode::t_combs

Namespaces
	riscv_i32_decode

Variables
constant integer	riscv_i32_decode::e32_force_enable =0
constant integer	riscv_i32_decode::i32m_force_disable =0
constant integer	riscv_i32_decode::i32_custom0_enable =0
constant integer	riscv_i32_decode::i32_custom1_enable =0
constant integer	riscv_i32_decode::i32_custom2_enable =0
constant integer	riscv_i32_decode::i32_custom3_enable =0