Control/status registers for a minimal RISC-V implementation. More...

Detailed Description

Control/status registers for a minimal RISC-V implementation.

Copyright: (C) 2016-2017, Gavin J Stark. All rights reserved.; Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0. Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

This file contains a module that implements the in-CPU CSRs required by a RISC-V implementation.

Data Structures
struct	riscv_csrs_minimal::t_csr_write

Variables
constant integer	riscv_csrs_minimal::mimpid = 0

constant integer	riscv_csrs_minimal::misa = 0

constant integer	riscv_csrs_minimal::mvendorid = 0

constant integer	riscv_csrs_minimal::mhartid = 0

constant integer	riscv_csrs_minimal::mstatus = 0

Data Structures