riscv_i32_pipeline_debug.cdl File Reference

Low-gate-count RISC-V pipeline debug module. More...

Detailed Description

Low-gate-count RISC-V pipeline debug module.

Copyright

(C) 2018, Gavin J Stark. All rights reserved.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0. Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

CDL implementation of minimal RISC-V teaching implementation

Data Structures
struct	riscv_i32_pipeline_debug::t_debug_combs
struct	riscv_i32_pipeline_debug::t_debug_state

Namespaces
	riscv_i32_pipeline_debug

Enumerations
enum	riscv_i32_pipeline_debug::t_debug_fsm {   riscv_i32_pipeline_debug::debug_fsm_running,   riscv_i32_pipeline_debug::debug_fsm_halting,   riscv_i32_pipeline_debug::debug_fsm_halted,   riscv_i32_pipeline_debug::debug_fsm_resuming }