riscv_modules.h File Reference

Header file for RISC-V implementations. More...

Detailed Description

Header file for RISC-V implementations.

Copyright

(C) 2016-2018, Gavin J Stark. All rights reserved.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0. Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Modules

module riscv_i32_debug	(	clock	clk,
		input bit	reset_n,
		input t_apb_request	apb_request,
		output t_apb_response	apb_response,
		output t_riscv_debug_mst	debug_mst,
		input t_riscv_debug_tgt	debug_tgt
	)

Parameters

clk	System clock
reset_n	Active low reset
apb_request	APB request
apb_response	APB response
debug_mst	Debug master to PDMs
debug_tgt	Debug target from PDMs

module riscv_i32_ifetch_debug	(	input t_riscv_fetch_req	pipeline_ifetch_req,
		output t_riscv_fetch_resp	pipeline_ifetch_resp,
		input t_riscv_i32_trace	pipeline_trace,
		input t_riscv_pipeline_debug_control	debug_control,
		output t_riscv_pipeline_debug_response	debug_response,
		output t_riscv_fetch_req	ifetch_req,
		input t_riscv_fetch_resp	ifetch_resp
	)

module riscv_i32_minimal	(	clock	clk,
		input bit	reset_n,
		input bit	proc_reset_n,
		input t_riscv_irqs	irqs,
		output t_riscv_mem_access_req	data_access_req,
		input t_riscv_mem_access_resp	data_access_resp,
		input t_sram_access_req	sram_access_req,
		output t_sram_access_resp	sram_access_resp,
		input t_riscv_config	riscv_config,
		output t_riscv_i32_trace	trace
	)

Parameters

[in]

irqs

Interrupts in to the CPU

module riscv_i32_minimal_apb	(	clock	clk,
		input bit	reset_n,
		input t_riscv_mem_access_req	data_access_req,
		output t_riscv_mem_access_resp	data_access_resp,
		output t_apb_request	apb_request,
		input t_apb_response	apb_response
	)

module riscv_i32_pipeline_debug	(	clock	clk,
		input bit	reset_n,
		input t_riscv_debug_mst	debug_mst,
		output t_riscv_debug_tgt	debug_tgt,
		output t_riscv_pipeline_debug_control	debug_control,
		input t_riscv_pipeline_debug_response	debug_response,
		input bit	rv_select[6]
	)

module riscv_i32_trace	(	clock	clk,
		input bit	reset_n,
		input t_riscv_i32_trace	trace
	)

Parameters

clk	Clock for the CPU
reset_n	Active low reset
trace	Trace signals

module riscv_i32c_pipeline	(	clock	clk,
		input bit	reset_n,
		input t_riscv_irqs	irqs,
		output t_riscv_fetch_req	ifetch_req,
		input t_riscv_fetch_resp	ifetch_resp,
		output t_riscv_mem_access_req	dmem_access_req,
		input t_riscv_mem_access_resp	dmem_access_resp,
		output t_riscv_i32_coproc_controls	coproc_controls,
		input t_riscv_i32_coproc_response	coproc_response,
		input t_riscv_config	riscv_config,
		output t_riscv_i32_trace	trace
	)

Parameters

irqs	Interrupts in to the CPU

module riscv_i32c_pipeline3	(	clock	clk,
		input bit	reset_n,
		input t_riscv_irqs	irqs,
		output t_riscv_fetch_req	ifetch_req,
		input t_riscv_fetch_resp	ifetch_resp,
		output t_riscv_mem_access_req	dmem_access_req,
		input t_riscv_mem_access_resp	dmem_access_resp,
		output t_riscv_i32_coproc_controls	coproc_controls,
		input t_riscv_i32_coproc_response	coproc_response,
		input t_riscv_config	riscv_config,
		output t_riscv_i32_trace	trace
	)

Parameters

irqs	Interrupts in to the CPU

module riscv_jtag_apb_dm	(	clock	jtag_tck,
		input bit	reset_n,
		input bit	ir[5],
		input t_jtag_action	dr_action,
		input	bitdr_in[50],
		output	bitdr_tdi_mask[50],
		output	bitdr_out[50],
		clock	apb_clock,
		output t_apb_request	apb_request,
		input t_apb_response	apb_response
	)

Parameters

jtag_tck	JTAG TCK signal, used as a clock
reset_n	Reset that drives all the logic
ir	JTAG IR which is to be matched against t_jtag_addr
dr_action	Action to perform with DR (capture or update, else ignore)
bitdr_in	Data register in; used in update, replaced by dr_out in capture, shift
bitdr_tdi_mask	One-hot mask indicating which DR bit TDI should replace (depends on IR)
bitdr_out	Data register out; same as data register in, except during capture when it is replaced by correct data dependent on IR, or shift when it goes right by one
apb_clock	APB clock signal, asynchronous to JTAG TCK
apb_request	APB request out
apb_response	APB response