riscv_minimal_debug

Detailed Description

Modules

module riscv_minimal_debug::riscv_minimal_debug	(	clock	clk,
		input bit	reset_n,
		output t_riscv_mem_access_req	dmem_access_req,
		input t_riscv_mem_access_resp	dmem_access_resp,
		output t_riscv_fetch_req	ifetch_req,
		input t_riscv_fetch_resp	ifetch_resp,
		input t_riscv_debug_mst	debug_mst,
		output t_riscv_debug_tgt	debug_tgt,
		input t_riscv_config	riscv_config,
		input bit	rv_select[6],
		output t_riscv_i32_trace	trace
	)

Parameters

[in]	debug_mst	Driven by debug module to all RISC-V cores
[out]	debug_tgt	Wired-or response bus from all RISC-V cores
[out]	trace