cpu6502.cdl File Reference

CDL implementation of 6502 CPU core. More...

Detailed Description

CDL implementation of 6502 CPU core.

Copyright

(C) 2016-2017, Gavin J Stark. All rights reserved.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0. Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

This is a (fairly) complete implementation of the original 6502 processor; currently it is missing the decimal mode for add, though.

The original 6502 is latch-based, using both levels of the clock.

This implementation is fully synchronous, running from a single clock edge (although it used to use two edges to match the 6502 behavior, this proved to be unnecessary).

Because of this, read and write controls, addresses and write data are valid at the start of a cycle, and read data is expected to be valid at the end of the cycle - i.e. an asynchronous RAM is required. This asynchronous behavior is best handled by having an intermediate clock edge (i.e. using a faster clock to generate the CPU clock and an SRAM clock, which alternate).

The BBC microcomputer effectively did just this, actually using one clock phase for CPU memory reads, and the other clock phase for video memory reads (oh for the days when memories were faster than logic...)

Data Structures
struct	cpu6502::t_flags
struct	cpu6502::t_interrupt_state
struct	cpu6502::t_state
struct	cpu6502::t_ir_decode
struct	cpu6502::t_mem_request
struct	cpu6502::t_useq_decode
struct	cpu6502::t_alu_result
struct	cpu6502::t_data_path

Namespaces
	cpu6502

Typedefs
typedef bit[src_en_num]	cpu6502::t_src_enables
typedef bit[src_wr_en_num]	cpu6502::t_src_write_enables
typedef bit[ids_en_num]	cpu6502::t_ids_enables

Enumerations
enum	cpu6502::t_src_enable {   cpu6502::src_en_acc = 0,   cpu6502::src_en_x = 1,   cpu6502::src_en_y = 2,   cpu6502::src_en_sp = 3,   cpu6502::src_en_psr = 4,   cpu6502::src_en_zero = 5,   cpu6502::src_en_pcl = 6,   cpu6502::src_en_pch = 7,   cpu6502::src_en_num = 8 }
enum	cpu6502::t_src_write_enable {   cpu6502::src_wr_en_acc = 0,   cpu6502::src_wr_en_x = 1,   cpu6502::src_wr_en_y = 2,   cpu6502::src_wr_en_sp = 3,   cpu6502::src_wr_en_psr = 4,   cpu6502::src_wr_en_flags = 5,   cpu6502::src_wr_en_num = 6 }
enum	cpu6502::t_ids_enable {   cpu6502::ids_en_pc = 0,   cpu6502::ids_en_src = 1,   cpu6502::ids_en_sp = 2,   cpu6502::ids_en_pch = 3,   cpu6502::ids_en_dl = 4,   cpu6502::ids_en_num = 5 }
enum	cpu6502::t_mem_data_src {   cpu6502::mem_data_src_src,   cpu6502::mem_data_src_pcl,   cpu6502::mem_data_src_pch,   cpu6502::mem_data_src_dl }
enum	cpu6502::t_dl_src {   cpu6502::dl_src_data,   cpu6502::dl_src_alu,   cpu6502::dl_src_hold }
enum	cpu6502::t_pc_op {   cpu6502::pc_op_hold,   cpu6502::pc_op_inc,   cpu6502::pc_op_branch_low,   cpu6502::pc_op_branch_high,   cpu6502::pc_op_jump,   cpu6502::pc_op_vector }
enum	cpu6502::t_useq_cycle {   cpu6502::cycle_decode,   cpu6502::cycle_fetch,   cpu6502::cycle_alu_complete,   cpu6502::cycle_calc_zp_offset,   cpu6502::cycle_read_zp,   cpu6502::cycle_read_zp_inc_adl,   cpu6502::cycle_read_zp_adl_address_calc_index,   cpu6502::cycle_alu,   cpu6502::cycle_write_zp,   cpu6502::cycle_read_high,   cpu6502::cycle_dl_inc,   cpu6502::cycle_read_dl_adl,   cpu6502::cycle_write_dl_adl,   cpu6502::cycle_write_adh_adl,   cpu6502::cycle_read_pch_pcl_indirect,   cpu6502::cycle_read_dl_inc_pc,   cpu6502::cycle_read_pch_pcl,   cpu6502::cycle_push_src,   cpu6502::cycle_push_psr,   cpu6502::cycle_push_pch,   cpu6502::cycle_push_pcl,   cpu6502::cycle_inc_sp,   cpu6502::cycle_read_sp,   cpu6502::cycle_read_sp_psr_from_dl,   cpu6502::cycle_read_sp_to_pch_pcl,   cpu6502::cycle_bcc_pcl,   cpu6502::cycle_bcc_pch_bwd,   cpu6502::cycle_bcc_pch_fwd }
enum	cpu6502::t_addressing_mode {   cpu6502::am_implied,   cpu6502::am_immediate,   cpu6502::am_zero_page,   cpu6502::am_absolute,   cpu6502::am_zero_indexed,   cpu6502::am_absolute_indexed,   cpu6502::am_indirect_x,   cpu6502::am_indirect_y,   cpu6502::am_branch,   cpu6502::am_brk,   cpu6502::am_rts,   cpu6502::am_rti,   cpu6502::am_jsr,   cpu6502::am_jump,   cpu6502::am_jump_indirect }
enum	cpu6502::t_interrupt_reason {   cpu6502::interrupt_reason_reset =0,   cpu6502::interrupt_reason_nmi =1,   cpu6502::interrupt_reason_irq =2,   cpu6502::interrupt_reason_brk =3 }
enum	cpu6502::t_ids_op {   cpu6502::ids_op_lsl,   cpu6502::ids_op_rol,   cpu6502::ids_op_lsr,   cpu6502::ids_op_ror,   cpu6502::ids_op_pass,   cpu6502::ids_op_pass_2,   cpu6502::ids_op_dec,   cpu6502::ids_op_inc }
enum	cpu6502::t_add_a_in_op {   cpu6502::add_a_in_op_pcl,   cpu6502::add_a_in_op_src,   cpu6502::add_a_in_op_zero }
enum	cpu6502::t_add_b_in_op {   cpu6502::add_b_in_op_dl,   cpu6502::add_b_in_op_ids,   cpu6502::add_b_in_op_not_ids }
enum	cpu6502::t_alu_op {   cpu6502::alu_op_or,   cpu6502::alu_op_and,   cpu6502::alu_op_bit,   cpu6502::alu_op_eor,   cpu6502::alu_op_a,   cpu6502::alu_op_b,   cpu6502::alu_op_adc,   cpu6502::alu_op_sbc,   cpu6502::alu_op_cmp,   cpu6502::alu_op_flags }