CDL Modules
srams.h
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1 
20 /*a Types */
21 /*t t_sram_access_req
22  */
23 typedef struct {
24  bit valid;
25  bit[4] id;
26  bit read_not_write;
27  bit[8] byte_enable;
28  bit[32] address;
29  bit[64] write_data;
30 } t_sram_access_req;
31 
32 /*t t_sram_access_resp
33  */
34 typedef struct {
35  bit ack;
36  bit valid;
37  bit[4] id;
38  bit[64] data;
39 } t_sram_access_resp;
40 
41 /*a Modules */
42 /*m se_sram_srw_128x64 */
43 extern module se_sram_srw_128x64( clock sram_clock,
44  input bit select,
45  input bit[7] address,
46  input bit read_not_write,
47  input bit write_enable,
48  input bit[64] write_data,
49  output bit[64] data_out )
50 {
51  timing to rising clock sram_clock select, address, read_not_write, write_data, write_enable;
52  timing from rising clock sram_clock data_out;
53 }
54 
55 /*m se_sram_srw_128x45 */
56 extern module se_sram_srw_128x45( clock sram_clock,
57  input bit select,
58  input bit[7] address,
59  input bit read_not_write,
60  input bit[45] write_data,
61  output bit[45] data_out )
62 {
63  timing to rising clock sram_clock select, address, read_not_write, write_data;
64  timing from rising clock sram_clock data_out;
65 }
66 
67 /*m se_sram_srw_256x7 */
68 extern module se_sram_srw_256x7( clock sram_clock,
69  input bit select,
70  input bit[8] address,
71  input bit read_not_write,
72  input bit[7] write_data,
73  output bit[7] data_out )
74 {
75  timing to rising clock sram_clock select, address, read_not_write, write_data;
76  timing from rising clock sram_clock data_out;
77 }
78 
79 /*m se_sram_srw_256x40 */
80 extern module se_sram_srw_256x40( clock sram_clock,
81  input bit select,
82  input bit[8] address,
83  input bit read_not_write,
84  input bit[40] write_data,
85  output bit[40] data_out )
86 {
87  timing to rising clock sram_clock select, address, read_not_write, write_data;
88  timing from rising clock sram_clock data_out;
89 }
90 
91 /*m se_sram_srw_16384x8 */
92 extern module se_sram_srw_16384x8( clock sram_clock,
93  input bit select,
94  input bit[14] address,
95  input bit read_not_write,
96  input bit write_enable,
97  input bit[8] write_data,
98  output bit[8] data_out )
99 {
100  timing to rising clock sram_clock select, address, read_not_write, write_data, write_enable;
101  timing from rising clock sram_clock data_out;
102 }
103 
104 /*m se_sram_srw_65536x8 */
105 extern module se_sram_srw_65536x8( clock sram_clock,
106  input bit select,
107  input bit[16] address,
108  input bit read_not_write,
109  input bit write_enable,
110  input bit[8] write_data,
111  output bit[8] data_out )
112 {
113  timing to rising clock sram_clock select, address, read_not_write, write_data, write_enable;
114  timing from rising clock sram_clock data_out;
115 }
116 
117 /*m se_sram_srw_16384x32 */
118 extern module se_sram_srw_16384x32( clock sram_clock,
119  input bit select,
120  input bit[14] address,
121  input bit write_enable,
122  input bit read_not_write,
123  input bit[32] write_data,
124  output bit[32] data_out )
125 {
126  timing to rising clock sram_clock select, address, read_not_write, write_data, write_enable;
127  timing from rising clock sram_clock data_out;
128 }
129 
130 /*m se_sram_srw_16384x32_we4 */
131 extern module se_sram_srw_16384x32_we8( clock sram_clock,
132  input bit select,
133  input bit[14] address,
134  input bit read_not_write,
135  input bit[4] write_enable,
136  input bit[32] write_data,
137  output bit[32] data_out )
138 {
139  timing to rising clock sram_clock select, address, read_not_write, write_data, write_enable;
140  timing from rising clock sram_clock data_out;
141 }
142 
143 /*m se_sram_srw_16384x40 */
144 extern module se_sram_srw_16384x40( clock sram_clock,
145  input bit select,
146  input bit[14] address,
147  input bit read_not_write,
148  input bit[40] write_data,
149  output bit[40] data_out )
150 {
151  timing to rising clock sram_clock select, address, read_not_write, write_data;
152  timing from rising clock sram_clock data_out;
153 }
154 
155 /*m se_sram_srw_32768x64 */
156 extern module se_sram_srw_32768x64( clock sram_clock,
157  input bit select,
158  input bit[15] address,
159  input bit read_not_write,
160  input bit write_enable,
161  input bit[64] write_data,
162  output bit[64] data_out )
163 {
164  timing to rising clock sram_clock select, address, read_not_write, write_data, write_enable;
165  timing from rising clock sram_clock data_out;
166 }
167 
168 /*m se_sram_srw_32768x32 */
169 extern module se_sram_srw_32768x32( clock sram_clock,
170  input bit select,
171  input bit[15] address,
172  input bit read_not_write,
173  input bit write_enable,
174  input bit[32] write_data,
175  output bit[32] data_out )
176 {
177  timing to rising clock sram_clock select, address, read_not_write, write_data, write_enable;
178  timing from rising clock sram_clock data_out;
179 }
180 
181 /*m se_sram_srw_65536x32 */
182 extern module se_sram_srw_65536x32( clock sram_clock,
183  input bit select,
184  input bit[16] address,
185  input bit read_not_write,
186  input bit write_enable,
187  input bit[32] write_data,
188  output bit[32] data_out )
189 {
190  timing to rising clock sram_clock select, address, read_not_write, write_data, write_enable;
191  timing from rising clock sram_clock data_out;
192 }
193 
194 /*m se_sram_mrw_2_16384x48 */
195 extern module se_sram_mrw_2_16384x48( clock sram_clock_0,
196  input bit select_0,
197  input bit[14] address_0,
198  input bit read_not_write_0,
199  input bit[48] write_data_0,
200  output bit[48] data_out_0,
201 
202  clock sram_clock_1,
203  input bit select_1,
204  input bit[14] address_1,
205  input bit read_not_write_1,
206  input bit[48] write_data_1,
207  output bit[48] data_out_1)
208 {
209  timing to rising clock sram_clock_0 select_0, address_0, read_not_write_0, write_data_0;
210  timing from rising clock sram_clock_0 data_out_0;
211  timing to rising clock sram_clock_1 select_1, address_1, read_not_write_1, write_data_1;
212  timing from rising clock sram_clock_1 data_out_1;
213 }
214 
215 /*m se_sram_mrw_2_16384x8 */
216 extern module se_sram_mrw_2_16384x8( clock sram_clock_0,
217  input bit select_0,
218  input bit[14] address_0,
219  input bit read_not_write_0,
220  input bit[8] write_data_0,
221  output bit[8] data_out_0,
222 
223  clock sram_clock_1,
224  input bit select_1,
225  input bit[14] address_1,
226  input bit read_not_write_1,
227  input bit[8] write_data_1,
228  output bit[8] data_out_1)
229 {
230  timing to rising clock sram_clock_0 select_0, address_0, read_not_write_0, write_data_0;
231  timing from rising clock sram_clock_0 data_out_0;
232  timing to rising clock sram_clock_1 select_1, address_1, read_not_write_1, write_data_1;
233  timing from rising clock sram_clock_1 data_out_1;
234 }
235 
se_sram_srw_32768x32
module se_sram_srw_32768x32(clock sram_clock, input bit select, input bit[15] address, input bit read_not_write, input bit write_enable, input bit[32] write_data, output bit[32] data_out)
Definition: srams.h:169
t_sram_access_resp::valid
bit valid
Definition: srams.h:36
se_sram_srw_16384x8
module se_sram_srw_16384x8(clock sram_clock, input bit select, input bit[14] address, input bit read_not_write, input bit write_enable, input bit[8] write_data, output bit[8] data_out)
Definition: srams.h:92
t_sram_access_req::id
bit[4] id
Definition: srams.h:25
t_sram_access_resp::ack
bit ack
Definition: srams.h:35
se_sram_srw_16384x32
module se_sram_srw_16384x32(clock sram_clock, input bit select, input bit[14] address, input bit write_enable, input bit read_not_write, input bit[32] write_data, output bit[32] data_out)
Definition: srams.h:118
se_sram_srw_256x7
module se_sram_srw_256x7(clock sram_clock, input bit select, input bit[8] address, input bit read_not_write, input bit[7] write_data, output bit[7] data_out)
Definition: srams.h:68
se_sram_srw_16384x40
module se_sram_srw_16384x40(clock sram_clock, input bit select, input bit[14] address, input bit read_not_write, input bit[40] write_data, output bit[40] data_out)
Definition: srams.h:144
se_sram_srw_32768x64
module se_sram_srw_32768x64(clock sram_clock, input bit select, input bit[15] address, input bit read_not_write, input bit write_enable, input bit[64] write_data, output bit[64] data_out)
Definition: srams.h:156
se_sram_mrw_2_16384x48
module se_sram_mrw_2_16384x48(clock sram_clock_0, input bit select_0, input bit[14] address_0, input bit read_not_write_0, input bit[48] write_data_0, output bit[48] data_out_0, clock sram_clock_1, input bit select_1, input bit[14] address_1, input bit read_not_write_1, input bit[48] write_data_1, output bit[48] data_out_1)
Definition: srams.h:195
t_sram_access_req::byte_enable
bit[8] byte_enable
Definition: srams.h:27
t_sram_access_req::valid
bit valid
Definition: srams.h:24
se_sram_srw_65536x32
module se_sram_srw_65536x32(clock sram_clock, input bit select, input bit[16] address, input bit read_not_write, input bit write_enable, input bit[32] write_data, output bit[32] data_out)
Definition: srams.h:182
t_sram_access_resp::data
bit[64] data
Definition: srams.h:38
se_sram_srw_256x40
module se_sram_srw_256x40(clock sram_clock, input bit select, input bit[8] address, input bit read_not_write, input bit[40] write_data, output bit[40] data_out)
Definition: srams.h:80
t_sram_access_req::write_data
bit[64] write_data
Definition: srams.h:29
se_sram_mrw_2_16384x8
module se_sram_mrw_2_16384x8(clock sram_clock_0, input bit select_0, input bit[14] address_0, input bit read_not_write_0, input bit[8] write_data_0, output bit[8] data_out_0, clock sram_clock_1, input bit select_1, input bit[14] address_1, input bit read_not_write_1, input bit[8] write_data_1, output bit[8] data_out_1)
Definition: srams.h:216
t_sram_access_req::read_not_write
bit read_not_write
Definition: srams.h:26
se_sram_srw_65536x8
module se_sram_srw_65536x8(clock sram_clock, input bit select, input bit[16] address, input bit read_not_write, input bit write_enable, input bit[8] write_data, output bit[8] data_out)
Definition: srams.h:105
se_sram_srw_128x64
module se_sram_srw_128x64(clock sram_clock, input bit select, input bit[7] address, input bit read_not_write, input bit write_enable, input bit[64] write_data, output bit[64] data_out)
Definition: srams.h:43
t_sram_access_resp
Definition: srams.h:34
se_sram_srw_128x45
module se_sram_srw_128x45(clock sram_clock, input bit select, input bit[7] address, input bit read_not_write, input bit[45] write_data, output bit[45] data_out)
Definition: srams.h:56
t_sram_access_req::address
bit[32] address
Definition: srams.h:28
t_sram_access_resp::id
bit[4] id
Definition: srams.h:37
se_sram_srw_16384x32_we8
module se_sram_srw_16384x32_we8(clock sram_clock, input bit select, input bit[14] address, input bit read_not_write, input bit[4] write_enable, input bit[32] write_data, output bit[32] data_out)
Definition: srams.h:131
t_sram_access_req
Definition: srams.h:23
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