Files
file	riscv_adjunct_de1_cl.cdl
	RISC-V adjunct for ARM AXI for the CL DE1 + daughterboard.

Detailed Description

Modules

module riscv_adjunct_de1_cl::riscv_adjunct_de1_cl	(	clock	clk,
		clock	video_clk,
		input bit	reset_n,
		input bit	video_locked,
		output t_de1_cl_lcd	lcd,
		input bit	keys[4],
		input bit	switches[10],
		output bit	leds[10],
		input t_ps2_pins	ps2_in,
		output t_ps2_pins	ps2_out,
		output bit	led_data_pin,
		input t_de1_cl_inputs_status	inputs_status,
		output t_de1_cl_inputs_control	inputs_control
	)

Parameters

[in]	clk	50MHz clock from DE1 clock generator
[in]	video_clk	9MHz clock from PLL, derived from 50MHz
[in]	reset_n	hard reset from a pin - a key on DE1
[in]	video_locked	High if video PLL has locked
[out]	lcd	LCD display out to computer lab daughterboard
[in]	keys	DE1 keys
[in]	switches	DE1 switches
[out]	leds	DE1 leds
[in]	ps2_in	PS2 input pins
[out]	ps2_out	PS2 output pin driver open collector
[out]	led_data_pin	DE1 CL daughterboard neopixel LED pin
[in]	inputs_status	DE1 CL daughterboard shifter register etc status
[out]	inputs_control	DE1 CL daughterboard shifter register control