23 include
"csr_interface.h" 25 include
"bbc_micro_types.h" 34 bit v_sync
"Asserted for the whole of the first scanline or a frame";
35 bit h_sync
"Asserted for a single clock at the start of every scanline";
36 bit will_h_sync
"Asserted if the next clock will be an @a h_sync";
37 bit v_displaying
"Asserted for a scanline if the scanline will display data";
38 bit display_required
"Asserted for scanlines being displayed, up to the end of the horizontal displayed area - permits prefetching of pixel data";
39 bit will_display_enable
"Asserted if the next clock will have @a display_enable asserted";
40 bit display_enable
"Asserted if pixels should be presented to the output (i.e. outside the front and back porches both horizontally and vertically)";
41 bit v_frame_last_line
"Asserted if ";
48 clock video_clk
"Video clock, used to generate vsync, hsync, data out, etc",
49 input bit reset_n
"Active low reset",
51 input
t_csr_request csr_request
"Pipelined CSR request interface to control the module",
52 output
t_csr_response csr_response
"Pipelined CSR response interface to control the module",
53 input bit[16] csr_select
"CSR select value to target this module on the CSR interface" 56 timing from rising clock video_clk video_timing;
58 timing to rising clock csr_clk csr_request, csr_select;
59 timing from rising clock csr_clk csr_response;
65 clock sram_clk
"SRAM write clock, with frame buffer data",
66 clock video_clk
"Video clock, used to generate vsync, hsync, data out, etc",
70 input bit[16] csr_select_in
"Tie to zero for default",
75 timing to rising clock sram_clk display_sram_write;
76 timing to rising clock csr_clk csr_select_in, csr_request;
77 timing from rising clock csr_clk csr_response;
78 timing from rising clock video_clk video_bus;
83 module
framebuffer( clock csr_clk
"Clock for CSR reads/writes",
84 clock sram_clk
"SRAM write clock, with frame buffer data",
85 clock video_clk
"Video clock, used to generate vsync, hsync, data out, etc",
91 input bit[16] csr_select
"CSR select value to target this module on the CSR interface" 94 timing to rising clock sram_clk display_sram_write;
95 timing to rising clock csr_clk csr_request, csr_select;
96 timing from rising clock csr_clk csr_response;
97 timing from rising clock video_clk video_bus;
Definition: csr_interface.h:61
Definition: framebuffer.h:33
Definition: csr_interface.h:82
Definition: bbc_micro_types.h:109
module framebuffer_timing(clock csr_clk, clock video_clk, input bit reset_n, output t_video_timing video_timing, input t_csr_request csr_request, output t_csr_response csr_response, input bit[16] csr_select)
Definition: framebuffer.h:47
module framebuffer_teletext(clock csr_clk, clock sram_clk, clock video_clk, input bit reset_n, input t_bbc_display_sram_write display_sram_write, output t_video_bus video_bus, input bit[16] csr_select_in, input t_csr_request csr_request, output t_csr_response csr_response)
Definition: framebuffer.h:64
module framebuffer(clock csr_clk, clock sram_clk, clock video_clk, input bit reset_n, input t_bbc_display_sram_write display_sram_write, output t_video_bus video_bus, input t_csr_request csr_request, output t_csr_response csr_response, input bit[16] csr_select)
Definition: framebuffer.h:83