118 timing from rising clock aclk ar, aw, w, bready, rready;
119 timing to rising clock aclk awready, arready, wready, b, r;
module axi_master(clock aclk, input bit areset_n, output t_axi_request ar, input bit awready, output t_axi_request aw, input bit arready, input bit wready, output t_axi_write_data w, output bit bready, input t_axi_write_response b, output bit rready, input t_axi_read_response r)
Definition: axi.h:104