CDL Modules
axi.h
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1 
22 /*a Types */
23 /*t t_axi_burst */
24 typedef enum[2] // 2 bits
25 {
30 } t_axi_burst;
31 
32 /*t t_axi_size */
33 typedef enum[3] // 3 bits
34 {
43 } t_axi_size;
44 
45 /*t t_axi_resp */
46 typedef enum[2] // 2 bits
47 {
52 } t_axi_resp;
53 
54 /*t t_axi_request */
55 typedef struct {
56  bit valid;
57  bit[12] id;
58  bit[32] addr;
59  bit[4] len;
62  bit[2] lock;
63  bit[4] cache;
64  bit[3] prot;
65  bit[4] qos;
66  bit[4] region;
67  bit[4] user;
69 
70 /*t t_axi_write_data */
71 typedef struct {
72  bit valid;
73  bit[12] id;
74  bit[32] data;
75  bit[4] strb;
76  bit last;
77  bit[4] user;
79 
80 /*t t_axi_write_response */
81 typedef struct {
82  bit valid;
83  bit[12] id;
85  bit[4] user;
87 
88 /*t t_axi_read_response */
92 typedef struct {
93  bit valid;
94  bit[12] id;
95  bit[32] data;
97  bit last;
98  bit[4] user;
100 
101 /*a Modules - see also apb_master_axi in apb.h*/
102 /*m axi_master */
103 extern
104 module axi_master(clock aclk,
105  input bit areset_n,
106  output t_axi_request ar,
107  input bit awready,
108  output t_axi_request aw,
109  input bit arready,
110  input bit wready,
111  output t_axi_write_data w,
112  output bit bready,
113  input t_axi_write_response b,
114  output bit rready,
115  input t_axi_read_response r
116  )
117 {
118  timing from rising clock aclk ar, aw, w, bready, rready;
119  timing to rising clock aclk awready, arready, wready, b, r;
120 }
t_axi_burst burst
Definition: axi.h:61
Definition: axi.h:50
Definition: axi.h:39
module axi_master(clock aclk, input bit areset_n, output t_axi_request ar, input bit awready, output t_axi_request aw, input bit arready, input bit wready, output t_axi_write_data w, output bit bready, input t_axi_write_response b, output bit rready, input t_axi_read_response r)
Definition: axi.h:104
t_axi_size size
Definition: axi.h:60
bit[4] qos
Definition: axi.h:65
Definition: axi.h:48
bit[4] user
Definition: axi.h:98
Definition: axi.h:42
bit last
Definition: axi.h:97
Definition: axi.h:81
Definition: axi.h:55
bit[4] user
Definition: axi.h:67
bit[4] len
Definition: axi.h:59
Definition: axi.h:36
bit[4] user
Definition: axi.h:77
Definition: axi.h:51
Definition: axi.h:40
Definition: axi.h:27
bit[12] id
Definition: axi.h:83
bit[4] cache
Definition: axi.h:63
Definition: axi.h:41
Definition: axi.h:28
Definition: axi.h:35
bit[12] id
Definition: axi.h:57
bit valid
Definition: axi.h:82
t_axi_size
Definition: axi.h:33
bit[4] strb
Definition: axi.h:75
Definition: axi.h:49
bit[32] data
Definition: axi.h:95
bit[12] id
Definition: axi.h:73
Definition: axi.h:38
bit last
Definition: axi.h:76
Definition: axi.h:29
bit valid
Definition: axi.h:56
t_axi_resp resp
Definition: axi.h:96
t_axi_resp
Definition: axi.h:46
t_axi_resp resp
Definition: axi.h:84
bit[4] region
Definition: axi.h:66
t_axi_burst
Definition: axi.h:24
Definition: axi.h:92
bit[12] id
Definition: axi.h:94
bit[2] lock
Definition: axi.h:62
Definition: axi.h:26
bit[32] addr
Definition: axi.h:58
Definition: axi.h:71
Definition: axi.h:37
bit valid
Definition: axi.h:93
bit valid
Definition: axi.h:72
bit[3] prot
Definition: axi.h:64
bit[32] data
Definition: axi.h:74
bit[4] user
Definition: axi.h:85