29 input bit clk_enable
"Assert to enable the internal clock; this permits I/O switches to easily use a slower clock",
30 input bit input_value,
31 output bit output_value,
32 input bit[16]
filter_period "Period over which to filter the input - the larger the value, the longer it takes to switch, but the more glitches are removed",
33 input bit[16]
filter_level "Value to exceed to switch output levels - the larger the value, the larger the hysteresis; must be less than filter_period" 36 timing to rising clock clk clk_enable;
38 timing from rising clock clk output_value;
module hysteresis_switch(clock clk, input bit reset_n, input bit clk_enable, input bit input_value, output bit output_value, input bit[16] filter_period, input bit[16] filter_level)
Definition: utils.h:27
constant integer filter_period
Definition: de1_cl_controls.cdl:29
constant integer filter_level
Definition: de1_cl_controls.cdl:30