Files
file	bbc_micro_de1_cl_bbc.cdl
	BBC microcomputer with RAMs for the CL DE1 + daughterboard.

Detailed Description

Modules

module bbc_micro_de1_cl_bbc::bbc_micro_de1_cl_bbc	(	clock	clk,
		clock	video_clk,
		input bit	reset_n,
		input bit	bbc_reset_n,
		input bit	framebuffer_reset_n,
		output t_bbc_clock_control	clock_control,
		input t_bbc_keyboard	bbc_keyboard,
		output t_video_bus	video_bus,
		input t_csr_request	csr_request,
		output t_csr_response	csr_response
	)

Clock that mirrors 2MHz falling - video data from RAM is valid at this edge, so used by CRTC, SAA5050 latches, SAA5050, vidproc

6502 clock, >=2MHz but extended when accessing 1MHz peripherals

Parameters

[in]	clk	50MHz clock from DE1 clock generator
[in]	video_clk	9MHz clock from PLL, derived from 50MHz
[in]	reset_n	hard reset from a pin - a key on DE1