125 module
csr_target_apb( clock clk
"Clock for the CSR interface, possibly gated version of master CSR clock",
126 input bit reset_n
"Active low reset",
127 input
t_csr_request csr_request
"Pipelined csr request interface input",
128 output
t_csr_response csr_response
"Pipelined csr request interface response",
131 input bit[16] csr_select
"Hard-wired select value for the client" 134 timing to rising clock clk csr_request, csr_select;
135 timing from rising clock clk csr_response;
137 timing from rising clock clk apb_request;
138 timing to rising clock clk apb_response;
147 module
csr_target_csr( clock clk
"Clock for the CSR interface, possibly gated version of master CSR clock",
148 input bit reset_n
"Active low reset",
149 input
t_csr_request csr_request
"Pipelined csr request interface input",
150 output
t_csr_response csr_response
"Pipelined csr request interface response",
151 output
t_csr_access csr_access
"Registered CSR access request to client",
152 input
t_csr_access_data csr_access_data
"Read data valid combinatorially based on csr_access",
153 input bit[16] csr_select
"Hard-wired select value for the client" 156 timing to rising clock clk csr_request, csr_select;
157 timing from rising clock clk csr_response;
159 timing from rising clock clk csr_access;
160 timing to rising clock clk csr_access_data;
169 module
csr_master_apb( clock clk
"Clock for the CSR interface; a superset of all targets clock",
170 input bit reset_n
"Active low reset",
173 input
t_csr_response csr_response
"Pipelined csr request interface response",
174 output
t_csr_request csr_request
"Pipelined csr request interface output" 177 timing to rising clock clk csr_response;
178 timing from rising clock clk csr_request;
180 timing to rising clock clk apb_request;
181 timing from rising clock clk apb_response;
192 module
csr_target_timeout( clock clk
"Clock for the CSR interface, possibly gated version of master CSR clock",
193 input bit reset_n
"Active low reset",
194 input
t_csr_request csr_request
"Pipelined csr request interface input",
195 output
t_csr_response csr_response
"Pipelined csr request interface response",
196 input bit[16] csr_timeout
"Number of cycles to wait for until auto-acknowledging a request" 199 timing to rising clock clk csr_request, csr_timeout;
200 timing from rising clock clk csr_response;
module csr_target_timeout(clock clk, input bit reset_n, input t_csr_request csr_request, output t_csr_response csr_response, input bit[16] csr_timeout)
Definition: csr_interface.h:192
Definition: csr_interface.h:61
bit[32] read_data
Definition: csr_interface.h:86
bit[16] select
Definition: csr_interface.h:64
Definition: csr_interface.h:82
bit[32] t_csr_access_data
Definition: csr_interface.h:115
bit read_data_error
Definition: csr_interface.h:85
bit read_data_valid
Definition: csr_interface.h:84
bit valid
Definition: csr_interface.h:62
bit[16] address
Definition: csr_interface.h:105
Definition: csr_interface.h:102
module csr_target_apb(clock clk, input bit reset_n, input t_csr_request csr_request, output t_csr_response csr_response, output t_apb_request apb_request, input t_apb_response apb_response, input bit[16] csr_select)
Definition: csr_interface.h:125
module csr_master_apb(clock clk, input bit reset_n, input t_apb_request apb_request, output t_apb_response apb_response, input t_csr_response csr_response, output t_csr_request csr_request)
Definition: csr_interface.h:169
bit[16] address
Definition: csr_interface.h:65
bit read_not_write
Definition: csr_interface.h:63
bit[32] data
Definition: csr_interface.h:106
bit acknowledge
Definition: csr_interface.h:83
bit read_not_write
Definition: csr_interface.h:104
bit valid
Definition: csr_interface.h:103
bit[32] data
Definition: csr_interface.h:66
module csr_target_csr(clock clk, input bit reset_n, input t_csr_request csr_request, output t_csr_response csr_response, output t_csr_access csr_access, input t_csr_access_data csr_access_data, input bit[16] csr_select)
Definition: csr_interface.h:147