BBC micro CDL submodules. More...

Detailed Description

BBC micro CDL submodules.

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Header file for the modules required for the BBC micro CDL implementation. It should probably be tidied up to put the SRAMs separately, and to start to pull together a cpu/peripheral CDL module header file of its own. But it will do for now

Modules

module acia6850	(	clock	clk,
		input bit	reset_n,
		input bit	read_not_write,
		input bit	chip_select[2],
		input bit	chip_select_n,
		input bit	address,
		input bit	data_in[8],
		output bit	data_out[8],
		output bit	irq_n,
		input bit	tx_clk,
		input bit	rx_clk,
		output bit	txd,
		input bit	cts,
		input bit	rxd,
		output bit	rts,
		input bit	dcd
	)

Parameters

clk	Clock that rises when the 'enable' of the 6850 completes - but a real clock for this model
read_not_write	Indicates a read transaction if asserted and chip selected
chip_select	Active high chip select
chip_select_n	Active low chip select
address	Changes during phase 1 (phi[0] high) with address to read or write
data_in	Data in (from CPU)
data_out	Read data out (to CPU)
irq_n	Active low interrupt
tx_clk	Clock used for transmit data - must be really about at most quarter the speed of clk
rx_clk	Clock used for receive data - must be really about at most quarter the speed of clk

module bbc_display	(	clock	clk,
		input t_bbc_display_sram_write	display_sram_write,
		input t_bbc_floppy_sram_request	floppy_sram_request,
		output t_bbc_keyboard	keyboard,
		output bit	reset_n,
		output t_bbc_floppy_sram_response	floppy_sram_response
	)

Parameters

clk	Clock running at 2MHz

module bbc_display_sram	(	clock	clk,
		input bit	reset_n,
		input t_bbc_display	display,
		output t_bbc_display_sram_write	sram_write,
		input t_csr_request	csr_request,
		output t_csr_response	csr_response
	)

Parameters

clk	Clock running at 2MHz

module bbc_floppy_sram	(	clock	clk,
		input bit	reset_n,
		input t_bbc_floppy_op	floppy_op,
		output t_bbc_floppy_response	floppy_response,
		output t_bbc_floppy_sram_request	sram_request,
		input t_bbc_floppy_sram_response	sram_response,
		input t_csr_request	csr_request,
		output t_csr_response	csr_response
	)

Parameters

clk	Clock running at 2MHz

module bbc_keyboard_csr	(	clock	clk,
		input bit	reset_n,
		output t_bbc_keyboard	keyboard,
		input bit	keyboard_reset_n,
		input t_csr_request	csr_request,
		output t_csr_response	csr_response
	)

Parameters

clk	Clock running at 2MHz

module bbc_keyboard_ps2	(	clock	clk,
		input bit	reset_n,
		input t_ps2_key_state	ps2_key,
		output t_bbc_keyboard	keyboard
	)

Parameters

clk	Clock of PS2 keyboard

module bbc_micro	(	clock	clk,
		input t_bbc_clock_control	clock_control,
		output t_bbc_clock_status	clock_status,
		input bit	reset_n,
		input t_bbc_keyboard	keyboard,
		output t_bbc_display	display,
		output bit	keyboard_reset_n,
		output t_bbc_floppy_op	floppy_op,
		input t_bbc_floppy_response	floppy_response,
		input t_bbc_micro_sram_request	host_sram_request,
		output t_bbc_micro_sram_response	host_sram_response
	)

Parameters

clk	Clock at least at '4MHz' - CPU runs at least half of this

module bbc_micro_clocking	(	clock	clk,
		input bit	reset_n,
		input t_bbc_clock_status	clock_status,
		output t_bbc_clock_control	clock_control,
		input t_csr_request	csr_request,
		output t_csr_response	csr_response
	)

Parameters

clk	4MHz clock in as a minimum

module bbc_micro_keyboard	(	clock	clk,
		input bit	reset_n,
		output bit	reset_out_n,
		input bit	keyboard_enable_n,
		input bit	column_select[4],
		input bit	row_select[3],
		output bit	key_in_column_pressed,
		output bit	selected_key_pressed,
		input t_bbc_keyboard	bbc_keyboard
	)

Parameters

reset_out_n	From the Break key
keyboard_enable_n	Asserted to make keyboard detection operate
column_select	Wired to pa[4;0], and indicates which column of the keyboard matrix to access
row_select	Wired to pa[3;4], and indicates which row of the keyboard matrix to access
key_in_column_pressed	Wired to CA2, asserted if keyboard_enable_n and a key is pressed in the specified column (other than row 0)
selected_key_pressed	Asserted if keyboard_enable_n is asserted and the selected key is pressed

module bbc_micro_rams	(	clock	clk,
		input bit	reset_n,
		input t_bbc_clock_control	clock_control,
		input t_bbc_micro_sram_request	host_sram_request,
		output t_bbc_micro_sram_response	host_sram_response,
		input t_bbc_display_sram_write	display_sram_write,
		input t_bbc_floppy_sram_request	floppy_sram_request,
		output t_bbc_floppy_sram_response	floppy_sram_response,
		output t_bbc_micro_sram_request	bbc_micro_host_sram_request,
		input t_bbc_micro_sram_response	bbc_micro_host_sram_response
	)

Parameters

clk	4MHz clock in as a minimum

module bbc_vidproc	(	clock	clk_cpu,
		clock	clk_2MHz_video,
		input bit	reset_n,
		input bit	chip_select_n,
		input bit	address,
		input bit	cpu_data_in[8],
		input bit	pixel_data_in[8],
		input bit	disen,
		input bit	invert_n,
		input bit	cursor,
		input bit	saa5050_red[6],
		input bit	saa5050_green[6],
		input bit	saa5050_blue[6],
		output bit	crtc_clock_enable,
		output bit	red[8],
		output bit	green[8],
		output bit	blue[8],
		output t_bbc_pixels_per_clock	pixels_valid_per_clock
	)

Parameters

[in]	clk_cpu	Output on real chip in a sense (2MHz out somewhat)
[in]	clk_2MHz_video	Output on real chip, 2MHz video clock
[in]	reset_n	Not present on the chip, but required for the model - power up reset
[in]	chip_select_n	Active low chip select
[in]	address	Valid with chip select
[in]	cpu_data_in	Data in (from CPU) - was combined with pixel_data_in in BBC micro to save pins
[in]	pixel_data_in	Data in (from RAM) - was combined with cpu_data_in in BBC micro to save pins
[in]	disen	Asserted by CRTC if black output required (e.g. during sync)
[in]	invert_n	Asserted (low) if the output should be inverted (post-disen probably)
[in]	cursor	Asserted for first character of a cursor
[in]	saa5050_red	3 pixels in at 2MHz, red component, from teletext
[in]	saa5050_green	3 pixels in at 2MHz, green component, from teletext
[in]	saa5050_blue	3 pixels out at 2MHz, blue component, from teletext
[out]	crtc_clock_enable	High for 2MHz, toggles for 1MHz - the 'character clock' - used also to determine when the shift register is loaded
[out]	red	8 pixels out at 2MHz, red component
[out]	green	8 pixels out at 2MHz, green component
[out]	blue	8 pixels out at 2MHz, blue component

module cpu6502	(	clock	clk,
		input bit	reset_n,
		input bit	ready,
		input bit	irq_n,
		input bit	nmi_n,
		output bit	ba,
		output bit	address[16],
		output bit	read_not_write,
		output bit	data_out[8],
		input bit	data_in[8]
	)

Parameters

clk	Clock, rising edge is start of phi1, end of phi2 - the phi1/phi2 boundary is not required
ready	Stops processor during current instruction. Does not stop a write phase. Address bus reflects current address being read. Stops the phase 2 from happening.
irq_n	Active low interrupt in
nmi_n	Active low non-maskable interrupt in
ba	Goes high during phase 2 if ready was low in phase 1 if read_not_write is 1, to permit someone else to use the memory bus
address	In real 6502, changes during phi 1 with address to read or write
read_not_write	In real 6502, changes during phi 1 with whether to read or write
data_out	In real 6502, valid at end of phi2 with data to write
data_in	Captured at the end of phi2 (rising clock in here)

module crtc6845	(	clock	clk_2MHz,
		clock	clk_1MHz,
		input bit	reset_n,
		output bit	ma[14],
		output bit	ra[5],
		input bit	read_not_write,
		input bit	chip_select_n,
		input bit	rs,
		input bit	data_in[8],
		output bit	data_out[8],
		input bit	lpstb_n,
		input bit	crtc_clock_enable,
		output bit	de,
		output bit	cursor,
		output bit	hsync,
		output bit	vsync
	)

Parameters

clk_1MHz	Clock that rises when the 'enable' of the 6845 completes - but a real clock for this model
ma	Memory address
ra	Row address
read_not_write	Indicates a read transaction if asserted and chip selected
chip_select_n	Active low chip select
rs	Register select - address line really
data_in	Data in (from CPU)
data_out	Data out (to CPU)
lpstb_n	Light pen strobe
crtc_clock_enable	Not on the real chip - really CLK - the character clock - but this is an enable for clk_2MHz

module fdc8271	(	clock	clk,
		input bit	reset_n,
		input bit	chip_select_n,
		input bit	read_n,
		input bit	write_n,
		input bit	address[2],
		input bit	data_in[8],
		output bit	data_out[8],
		output bit	irq_n,
		output bit	data_req,
		input bit	data_ack_n,
		output bit	select[2],
		input bit	ready[2],
		output bit	fault_reset,
		output bit	write_enable,
		output bit	seek_step,
		output bit	direction,
		output bit	load_head,
		output bit	low_current,
		input bit	track_0_n,
		input bit	write_protect_n,
		input bit	index_n,
		output t_bbc_floppy_op	bbc_floppy_op,
		input t_bbc_floppy_response	bbc_floppy_response
	)

Parameters

reset_n	8271 has an active high reset, but...
chip_select_n	Active low chip select
read_n	Indicates a read transaction if asserted and chip selected
write_n	Indicates a write transaction if asserted and chip selected
address	Address of register being accessed
data_in	Data in (from CPU)
data_out	Read data out (to CPU)
irq_n	Was INT on the 8271, but that means something else now; active low interrupt
select	drive select
ready	drive ready
write_enable	High if the drive should write data
seek_step	High if the drive should step
direction	Direction of step
load_head	Enable drive head
low_current	Asserted for track>=43
track_0_n	Asserted low if the selected drive is on track 0
write_protect_n	Asserted low if the selected drive is write-protected
index_n	Asserted low if the selected drive photodiode indicates start of track
bbc_floppy_op	Model drive operation, including write data
bbc_floppy_response	Parallel data read, specific to the model

module saa5050	(	clock	clk_2MHz,
		input bit	clk_1MHz_enable,
		input bit	reset_n,
		input bit	superimpose_n,
		input bit	data_n,
		input bit	data_in[7],
		input bit	dlim,
		input bit	glr,
		input bit	dew,
		input bit	crs,
		input bit	bcs_n,
		output bit	tlc_n,
		input bit	lose,
		input bit	de,
		input bit	po,
		output bit	red[6],
		output bit	green[6],
		output bit	blue[6],
		output bit	blan,
		input t_bbc_micro_sram_request	host_sram_request
	)

Parameters

clk_2MHz	Supposedly 6MHz pixel clock (TR6), except we use 2MHz and deliver 3 pixels per tick; rising edge should be coincident with clk_1MHz edges
clk_1MHz_enable	Clock enable high for clk_2MHz when the SAA's 1MHz would normally tick
superimpose_n	Not implemented
data_n	Serial data in, not implemented
data_in	Parallel data in
dlim	clocks serial data in somehow (datasheet is dreadful...)
glr	General line reset - can be tied to hsync - assert once per line before data comes in
dew	Data entry window - used to determine flashing rate and resets the ROM decoders - can be tied to vsync
crs	Character rounding select - drive high on even interlace fields to enable use of rounded character data (kinda indicates 'half line')
bcs_n	Assert (low) to enable double-height characters (?)
tlc_n	Asserted (low) when double-height characters occur (?)
lose	Load output shift register enable - must be low before start of character data in a scanline, rising with (or one tick earlier?) the data; changes off falling F1, rising clk_1MHz
de	Display enable
po	Picture on
host_sram_request	Write only, writes on clk_2MHz rising, acknowledge must be handled by supermodule

module via6522	(	clock	clk,
		clock	clk_io,
		input bit	reset_n,
		input bit	read_not_write,
		input bit	chip_select,
		input bit	chip_select_n,
		input bit	address[4],
		input bit	data_in[8],
		output bit	data_out[8],
		output bit	irq_n,
		input bit	ca1,
		input bit	ca2_in,
		output bit	ca2_out,
		output bit	pa_out[8],
		input bit	pa_in[8],
		input bit	cb1,
		input bit	cb2_in,
		output bit	cb2_out,
		output bit	pb_out[8],
		input bit	pb_in[8]
	)

Parameters

clk	1MHz clock rising when bus cycle finishes
clk_io	1MHz clock rising when I/O should be captured - can be antiphase to clk
read_not_write	Indicates a read transaction if asserted and chip selected
chip_select	Active high chip select
chip_select_n	Active low chip select
address	Changes during phase 1 (phi[0] high) with address to read or write
data_in	Data in (from CPU)
data_out	Read data out (to CPU)
irq_n	Active low interrupt
ca1	Port a control 1 in
ca2_in	Port a control 2 in
ca2_out	Port a control 2 out
pa_out	Port a data out
pa_in	Port a data in
cb1	Port b control 1 in
cb2_in	Port b control 2 in
cb2_out	Port b control 2 out
pb_out	Port b data out
pb_in	Port b data in